Senior SoC STA Engineer: Timing, Clocking & Optimization

Intel; Santa Clara (CA); Hybrid; USD 164,000 - 269,000; Full time

Job summary

Intel is seeking an experienced Senior Static Timing Analysis (STA) Engineer to guide the development of next-generation SoCs. You will collaborate with architecture, logic design, clocking, DFT, and physical design teams to ensure timing convergence, signal integrity, and optimal performance across complex designs.

The role offers a hybrid work model with locations including Phoenix, AZ and Santa Clara, CA, and provides opportunities to influence methodologies, tool flows, and best practices

Qualifications

• Bachelor's degree in Computer Engineering, Computer Science, or related STEM discipline.
• Master's degree in the same fields.
• PhD in related field (preferred).
• 5+ years of industry experience in STA, clock networks, timing closure.

Responsibilities

• Perform SOC level timing analysis and optimization.
• Generate and verify timing constraints for SoCs.
• Develop optimized clock networks for performance and power.
• Define methodologies for high-quality timing models.
• Establish PVT conditions for timing analysis and binning.

Skills

Static timing analysis

Clock network design

Timing closure

Timing constraints

Physical design knowledge

Optimization techniques

TCL scripting

Timing analysis tools

Extraction tools

Physical design tools

Education

Bachelor's degree in Computer Engineering, Computer Science, or related STEM discipline

Master's degree in the same fields

PhD in related field

Tools

Timing analysis tools

Extraction tools

Physical design tools

Job description

Intel is seeking an experienced Senior Static Timing Analysis (STA) Engineer to guide the development of next-generation SoCs. You will collaborate with architecture, logic design, clocking, DFT, and physical design teams to ensure timing convergence, signal integrity, and optimal performance across complex designs.

The role offers a hybrid work model with locations including Phoenix, AZ and Santa Clara, CA, and provides opportunities to influence methodologies, tool flows, and best practices