Senior STA Lead for High-Performance AI ASICs

Google; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google is seeking an experienced Static Timing Analysis (STA) leader to shape the timing closure for high-performance ASICs and TPU integration. You will drive timing constraints, margins, and ECOs across large compute designs and collaborate with RTL, DFT, and architecture teams to meet tight deadlines.

The role emphasizes cross-team collaboration, scalable STA methodologies, and the delivery of robust timing sign-off for next-generation TPU hardware, with a strong focus on silicon accuracy and

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 10 years of STA experience with 5 years in a technical leadership role.
• Experience achieving full-chip timing convergence and handling timing constraints (SDC).
• Proficiency with Tcl for timing analysis, closure, extraction, noise, or crosstalk.
• Experience with EDA tools such as PrimeTime, Tempus, Timevision, STAR-RC.
• Experience analyzing cross-chip clock distribution networks.

Responsibilities

• Lead timing constraint creation and validation, ECO creation, and final timing sign-off for complex ASICs.
• Drive STA methodology development for chip implementation and timing signoff.
• Develop and support flows around industry-standard STA and parasitic extraction tools.
• Triage and resolve tool-related technical issues with EDA vendors and teams.
• Collaborate with RTL design and DFT teams for high-quality timing constraints.

Skills

STA expertise

Technical leadership

Timing constraints

Tcl scripting

EDA tools

Cross-chip clock networks

Education

Bachelor's degree in EE/CE/CS

Master's/PhD in EE/CE/CS (preferred)

Tools

PrimeTime

Tempus

Timevision

STAR-RC

Job description

Google is seeking an experienced Static Timing Analysis (STA) leader to shape the timing closure for high-performance ASICs and TPU integration. You will drive timing constraints, margins, and ECOs across large compute designs and collaborate with RTL, DFT, and architecture teams to meet tight deadlines.

The role emphasizes cross-team collaboration, scalable STA methodologies, and the delivery of robust timing sign-off for next-generation TPU hardware, with a strong focus on silicon accuracy and