Timing Implementation Engineer: PCIe STA & Sign-off

Sintegra Inc.; California (MO); On-site; USD 110,000 - 170,000; Full time

Job summary

Sintegra Inc. seeks an experienced Timing Implementation Engineer to drive block-level and full-chip STA from RTL synthesis through tapeout. You’ll write SDC timing constraints for PCIe and other high-speed interfaces, build robust timing methodology, and collaborate with architects to ensure sign-off.

Ideal candidate has 5+ years in STA and synthesis, hands-on experience with PrimeTime and Design Compiler/Fusion Compiler, and a strong track record of timing closure in advanced processes.

Qualifications

• Bachelor’s degree in EE/CE or related field.
• 5+ years of industry experience, with at least 3 years focused on STA and synthesis/timing closure.
• Hands-on with PrimeTime and Design Compiler/Fusion Compiler (or equivalent).
• Proven experience writing and debugging timing constraints (SDC) for PCIe or other high-speed protocols.
• Strong collaboration with physical design and architecture teams.

Responsibilities

• Perform block-level and full-chip STA across the project lifecycle from investigation to tapeout.
• Execute RTL synthesis flows, ensuring QoR and alignment with timing constraints.
• Write and develop timing constraints (SDC) for PCIe and other high-speed interfaces.
• Build and enhance timing methodology and infrastructure through synthesis to closure.
• Collaborate with architects and logic designers to generate accurate block and chip-level constraints.
• Define analysis scenarios and margining strategies with system and technology teams.
• Partner with physical design teams to achieve timing closure and silicon sign-off.

Skills

Static Timing Analysis

RTL synthesis

Timing closure

PCIe interfaces

Tapeout sign-off

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Synopsys PrimeTime

Design Compiler/Fusion Compiler

Job description

Sintegra Inc. seeks an experienced Timing Implementation Engineer to drive block-level and full-chip STA from RTL synthesis through tapeout. You’ll write SDC timing constraints for PCIe and other high-speed interfaces, build robust timing methodology, and collaborate with architects to ensure sign-off.

Ideal candidate has 5+ years in STA and synthesis, hands-on experience with PrimeTime and Design Compiler/Fusion Compiler, and a strong track record of timing closure in advanced processes.