STA Engineer

Stellar IT Solutions LLC; San Jose (TX); Vor Ort; USD 120.000 - 190.000; Vollzeit

Zusammenfassung

Stellar IT Solutions LLC is seeking a seasoned STA Engineer to lead timing analysis, closure, and sign-off for complex ASIC/SoC designs. You will work closely with RTL, synthesis, and physical-design teams in a fast-paced environment.

The role requires hands-on experience with STA, timing constraints, MCMM, and ECO timing optimization, using tools like Synopsys PrimeTime. Collaboration and scripting with Tcl are essential for success.

Qualifikationen

• Experience in STA for complex ASIC/SoC designs.
• Strong knowledge of setup/hold analysis.
• Hands-on with SDC constraints.
• Experience with MCMM timing analysis.
• Ability to drive timing closure and ECOs.
• Collaborates with RTL, synthesis, and physical design teams.

Aufgaben

• Perform Static Timing Analysis for complex designs.
• Analyze setup, hold, recovery, and removal violations.
• Develop and validate timing constraints.
• Perform MCMM timing analysis.
• Debug timing violations and drive timing closure.
• Analyze clock definitions, generated clocks, timing exceptions.
• Work with RTL, synthesis, and physical design teams.
• Support ECO implementation and timing optimization.
• Generate and analyze timing reports.

Kenntnisse

STA

timing-closure

Timing analysis

MCMM analysis

timing constraints

synthesis

physical design

RTL collaboration

ECO timing

Tcl scripting

Tools

Synopsys PrimeTime

Jobbeschreibung

Job Title: STA Engineer
Interview: Virtual
Job Duration: Long Term Contract
Job Location: Austin, TX OR Bay Area, CA
Job Description

We are looking for experienced STA Engineers responsible for timing analysis, timing closure, and sign-off of complex ASIC/SoC designs. The ideal candidate will have strong hands-on experience in Static Timing Analysis, timing constraints, MCMM analysis, and timing closure, along with a solid understanding of synthesis and physical-design flows.

Key Responsibilities

• Perform Static Timing Analysis (STA) for complex designs.
• Analyze setup, hold, recovery, and removal violations.
• Develop and validate timing constraints.
• Perform MCMM timing analysis.
• Debug timing violations and drive timing closure.
• Analyze clock definitions, generated clocks, and timing exceptions.
• Work closely with RTL, synthesis, and physical design teams.
• Support ECO implementation and timing optimization.
• Generate and analyze timing reports.

Required Skills

• Strong STA and timing-closure experience.
• Hands-on experience with Synopsys PrimeTime or equivalent.
• Strong knowledge of SDC.
• Strong understanding of setup/hold analysis.
• Experience with MCMM.
• Strong knowledge of timing constraints.
• Tcl scripting experience.
• Understanding of synthesis and physical-design flows.