Senior STA Engineer — Timing Closure for ASIC/SoC Designs

Stellar IT Solutions LLC; San Jose (TX); On-site; USD 120,000 - 190,000; Full time

Job summary

Stellar IT Solutions LLC is seeking a seasoned STA Engineer to lead timing analysis, closure, and sign-off for complex ASIC/SoC designs. You will work closely with RTL, synthesis, and physical-design teams in a fast-paced environment.

The role requires hands-on experience with STA, timing constraints, MCMM, and ECO timing optimization, using tools like Synopsys PrimeTime. Collaboration and scripting with Tcl are essential for success.

Qualifications

• Experience in STA for complex ASIC/SoC designs.
• Strong knowledge of setup/hold analysis.
• Hands-on with SDC constraints.
• Experience with MCMM timing analysis.
• Ability to drive timing closure and ECOs.
• Collaborates with RTL, synthesis, and physical design teams.

Responsibilities

• Perform Static Timing Analysis for complex designs.
• Analyze setup, hold, recovery, and removal violations.
• Develop and validate timing constraints.
• Perform MCMM timing analysis.
• Debug timing violations and drive timing closure.
• Analyze clock definitions, generated clocks, timing exceptions.
• Work with RTL, synthesis, and physical design teams.
• Support ECO implementation and timing optimization.
• Generate and analyze timing reports.

Skills

STA

timing-closure

Timing analysis

MCMM analysis

timing constraints

synthesis

physical design

RTL collaboration

ECO timing

Tcl scripting

Tools

Synopsys PrimeTime

Job description

Stellar IT Solutions LLC is seeking a seasoned STA Engineer to lead timing analysis, closure, and sign-off for complex ASIC/SoC designs. You will work closely with RTL, synthesis, and physical-design teams in a fast-paced environment.

The role requires hands-on experience with STA, timing constraints, MCMM, and ECO timing optimization, using tools like Synopsys PrimeTime. Collaboration and scripting with Tcl are essential for success.