Senior STA Engineer — Low-Power SoC Timing Lead

Efficient Computer; Pittsburgh (Allegheny County); On-site; USD 200,000 - 250,000; Full time

Benefits offered by this job

Equity compensation

Comprehensive benefits

401K match

Job summary

Efficient is seeking a Lead STA Engineer to join our hardware team in Pittsburgh, PA. The Timing Lead will drive timing convergence for a finfet, multi-patterning tech and oversee IP/SOC timing from design to sign-off.

You will collaborate with RTL, DFT and IP vendors to optimize constraints and create robust CAD flows. This role offers equity and a comprehensive benefits package in a fast-moving, edge-computing environment.

Qualifications

• Master's degree in Electrical Engineering with 5+ years of industry experience.
• PhD in Electrical Engineering with 3+ years of industry experience.
• Proven track record of delivering STA sign-off for multiple tape-outs in 12nm or below process technologies.
• Experience with EDA flow using Cadence/Synopsys/Mentor tools for STA/simulations (PT/Hspice) with hierarchical design and abstraction techniques.
• Hands-on experience in timing convergence of high-frequency and low power designs.
• Excellent scripting skills in TCL, shell and python.

Responsibilities

• Drive and develop Timing flows, methodology for state of the art finfet and multi patterning based technologies from scratch in Cadence Tempus or Synopsys Primetime.
• Own and drive timing convergence of IP, Subsystem and SOC blocks.
• Define timing margining, PVTRC corner definitions, extraction methodology , signoff timing to SYN/PNR correlation.
• Develop slew rate, glitch noise checks to ensure robust design quality.
• Develop custom timing checks as pertains to Efficient's proprietary Ultra low power architecture.
• Work closely with RTL team, DFT and IP vendors to define and drive SDC constraints.
• Have an in-depth understanding of all collaterals for all hard and soft IPs used by the design.
• Partner with post-si products bring up team to ensure good pre-si to post-si correlation from a timing perspective.
• Work with 3rd party vendor resources and coordinate their work in the timing domain.
• Continuously work on improving flow consistency and efficiency in the context of multiple product type swim lanes.

Skills

STA sign-off

Timing convergence

Low power design

Scripting: TCL

Scripting: Python

Shell scripting

SoC timing

Education

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence

Synopsys

Mentor

HSPICE

PT

Job description

Efficient is seeking a Lead STA Engineer to join our hardware team in Pittsburgh, PA. The Timing Lead will drive timing convergence for a finfet, multi-patterning tech and oversee IP/SOC timing from design to sign-off.

You will collaborate with RTL, DFT and IP vendors to optimize constraints and create robust CAD flows. This role offers equity and a comprehensive benefits package in a fast-moving, edge-computing environment.