Senior Timing Lead Engineer – Ultra-Low-Power SoC

Efficient Computer; San Jose (CA); On-site; USD 200,000 - 250,000; Full time

Benefits offered by this job

401K match

Company-paid benefits

Equity program

Paid parental leave

Flexibility

Job summary

Efficient Computer in San Jose is looking for a Lead STA Engineer to drive timing convergence for their innovative energy-efficient processor. In this cross-functional role, you'll work on cutting-edge fin-FET technologies while collaborating with a team of world-class engineers.

Ideal candidates will have a Master's or PhD in Electrical Engineering, alongside substantial experience in static timing analysis and low-power design. Efficient offers a competitive salary between $200,000 to $250,000 and comprehensive benefits.

Qualifications

• 5+ years of industry experience or 3+ years with a PhD in Electrical Engineering.
• Proven track record in delivering IP STA sign-off.
• Hands-on experience in timing convergence of designs.

Responsibilities

• Develop timing flows and methodology from scratch.
• Own timing convergence for various SOC blocks.
• Define timing margining and extraction methodology.

Skills

Static timing analysis

Scripting in Tcl

Low-power design techniques

High-frequency designs

Education

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Tempus

Synopsys Primetime

Hspice

Job description

Efficient Computer in San Jose is looking for a Lead STA Engineer to drive timing convergence for their innovative energy-efficient processor. In this cross-functional role, you'll work on cutting-edge fin-FET technologies while collaborating with a team of world-class engineers.

Ideal candidates will have a Master's or PhD in Electrical Engineering, alongside substantial experience in static timing analysis and low-power design. Efficient offers a competitive salary between $200,000 to $250,000 and comprehensive benefits.