Senior STA Engineer: SoC Timing, Clocking & Power

Intel Corporation; Phoenix, Northern (AZ, KY); Hybrid; USD 164,000 - 269,000; Full time

Benefits offered by this job

Hybrid work model

Health benefits

Stock bonuses

Retirement plan

Vacation

Job summary

Intel Corporation in the United States is seeking an experienced Senior Static Timing Analysis (STA) Engineer to help drive next-generation SoC designs that power industry-leading technologies. You will collaborate across architecture, logic, clocking, DFT, and physical design teams to ensure timing convergence, signal integrity, and product readiness.

The role offers a hybrid work model with on-site Phoenix presence and opportunities to influence methodologies, tool flows, and engineering best

Qualifications

• Bachelor's degree in Computer Engineering, CS, or related STEM with 6+ years experience.
• Master's degree with 4+ years experience.
• 5+ years experience in SOC timing analysis, clock network design, and timing closure.
• Experience with TCL scripting and timing budgeting processes.

Responsibilities

• Perform SOC level timing analysis and optimization to meet requirements.
• Generate and verify timing constraints and address violations.
• Develop optimized clock networks for performance and power efficiency.
• Define timing models and enable efficient physical design.
• Establish appropriate PVT conditions for timing analysis.
• Collaborate with architecture, clocking, DFT, and design teams.
• Contribute to tool/flow development for SoC timing processes.

Skills

SOC timing analysis

Clock network design

Timing closure

TCL scripting

Education

Bachelor's degree in Computer Engineering, Computer Science, or related STEM

Master's degree in related fields

Tools

Industry-standard tools for timing analysis

Physical design tools

Job description

Intel Corporation in the United States is seeking an experienced Senior Static Timing Analysis (STA) Engineer to help drive next-generation SoC designs that power industry-leading technologies. You will collaborate across architecture, logic, clocking, DFT, and physical design teams to ensure timing convergence, signal integrity, and product readiness.

The role offers a hybrid work model with on-site Phoenix presence and opportunities to influence methodologies, tool flows, and engineering best