Lead STA Engineer

Efficient Computer; Pittsburgh (Allegheny County); On-site; USD 200,000 - 250,000; Full time

Benefits offered by this job

Equity compensation

Comprehensive benefits

401K match

Job summary

Efficient is seeking a Lead STA Engineer to join our hardware team in Pittsburgh, PA. The Timing Lead will drive timing convergence for a finfet, multi-patterning tech and oversee IP/SOC timing from design to sign-off.

You will collaborate with RTL, DFT and IP vendors to optimize constraints and create robust CAD flows. This role offers equity and a comprehensive benefits package in a fast-moving, edge-computing environment.

Qualifications

• Master's degree in Electrical Engineering with 5+ years of industry experience.
• PhD in Electrical Engineering with 3+ years of industry experience.
• Proven track record of delivering STA sign-off for multiple tape-outs in 12nm or below process technologies.
• Experience with EDA flow using Cadence/Synopsys/Mentor tools for STA/simulations (PT/Hspice) with hierarchical design and abstraction techniques.
• Hands-on experience in timing convergence of high-frequency and low power designs.
• Excellent scripting skills in TCL, shell and python.

Responsibilities

• Drive and develop Timing flows, methodology for state of the art finfet and multi patterning based technologies from scratch in Cadence Tempus or Synopsys Primetime.
• Own and drive timing convergence of IP, Subsystem and SOC blocks.
• Define timing margining, PVTRC corner definitions, extraction methodology , signoff timing to SYN/PNR correlation.
• Develop slew rate, glitch noise checks to ensure robust design quality.
• Develop custom timing checks as pertains to Efficient's proprietary Ultra low power architecture.
• Work closely with RTL team, DFT and IP vendors to define and drive SDC constraints.
• Have an in-depth understanding of all collaterals for all hard and soft IPs used by the design.
• Partner with post-si products bring up team to ensure good pre-si to post-si correlation from a timing perspective.
• Work with 3rd party vendor resources and coordinate their work in the timing domain.
• Continuously work on improving flow consistency and efficiency in the context of multiple product type swim lanes.

Skills

STA sign-off

Timing convergence

Low power design

Scripting: TCL

Scripting: Python

Shell scripting

SoC timing

Education

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence

Synopsys

Mentor

HSPICE

PT

Job description

San Jose, CA OR Pittsburgh, PA OR Austin, TX

Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution

Efficient is seeking a Lead STA Engineer to join our growing team. The Timing Lead will work on timing convergence and methodology hands on for the world’smost energy-efficient, general-purpose processor. This role will be in the newly formed hardware engineering group and will focus on designing in state of the art finfet technologies. The role is cross functional and we are a integrated highly interdisciplinary team of world class engineers.

This is a unique opportunity to get in at the early stages of a hardware engineering organization and have influence on our products as we move from initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!

Key Responsibilities

• Drive and develop Timing flows, methodology for state of the art finfet and multi patterning based technologies from scratch in Cadence Tempus or Synopsys Primetime.
• Own and drive timing convergence of IP, Subsystem and SOC blocks.
• Define timing margining, PVTRC corner definitions, extraction methodology , signoff timing to SYN/PNR correlation.
• Develop slew rate, glitch noise checks to ensure robust design quality.
• Develop custom timing checks as pertains to Efficients proprietary Ultra low power architecture.
• Work closely with RTL team, DFT and IP vendors to define and drive SDC constraints.
• Have an in-depth understanding of all collaterals for all hard and soft IPs used by the design.
• Partner with post-si products bring up team to ensure good pre-si to post-si correlation from a timing perspective.
• Work with 3rd party vendor resources and coordinate their work in the timing domain.
• Continuously work on improving flow consistency and efficiency in the context of multiple product type swim lanes.

Required Qualifications

• Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience
• Proven track record of delivering IP/SS (or SoC) STA sign-off for multiple tape-outs in 12nm or below process technologies.
• Experience with EDA flow using Cadence/Synopsys/Mentor tools for STA/simulations (PT/Hspice) with hierarchical design and abstraction techniques
• Hands-on experience in timing convergence of high-frequency and low power designs.
• Expert knowledge of static timing analysis, defining constraints and exceptions, corners/voltage definitions and timing margining.
• Experience with low power implementation typical in industry and how timing convergence impacts power draw ensuring we are making optimal tradeoffs.
• Excellent scripting skills in TCL, shell and python.

Desired Qualifications

• Knowledge of computer architecture
• Knowledge of physical design and ASIC implementation
• Experience in full chip sign-off budgeting
• Knowledge of circuit design, device physics, deep sub-micron technology, and SOI technology and its implications to physical design
• Proficiency with industry-grade physical design flow and hands-on building CAD flow infrastructure for PD engineers.
• Definition of design constraints for static timing analysis (synthesis, pre/post‑cts, sign‑off) and corners/voltage definitions.
• Experience in integrating analog or mixed-signal macro on top-level design.

We offer a competitive salary for this role, generally ranging from $200,000 to $250,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.

Why Join Efficient?

Efficient offers acompetitive compensation and benefits package, including401K match, company-paid benefits, equity program, paid parental leave, and flexibility. We are committed to personal and professional development and strive to grow together as people and as a company.