STA & Constraints Engineer – Timing Closure Expert

Advanced Micro Devices; Santa Clara (CA); On-site; USD 150,000 - 185,000; Full time

Job summary

Advanced Micro Devices in Santa Clara, CA is seeking a STA/Constraints Engineer to develop full-chip constraints and drive timing closure. You’ll collaborate with Fellows, Principal Engineers, Architects, and cross-functional teams across Physical Design, Timing Analysis, Synthesis, and Power signoff to deliver reliable FCT closure.

The role requires deep experience in STA, constraints, DFT timing concepts, and proficient scripting with Perl/TCL/Python.

Qualifications

• Industry experience in STA, constraints, timing signoff and physical design.
• Expert user of industry-standard PD tools like SNPS PT/GCA (must) and ICC2/FC (desired).
• Good experience and understanding of DFT timing concepts, MBIST, Top level clock implementation, Place and Route flows - floorplanning and placement, CTS and Route.
• Good experience with Perl/TCL/Shell/Python scripting, and Verilog RTL design.
• Excellent presentation and inter-communication skills.
• Experience with Verilog RTL design/implementation and has experience of large digital ASIC project.
• Experience with physical design is a plus.
• Has Synthesis or physical implement experience.
• Experience with lower power design methodology.
• Good English skills on talking, presentation and writing documents.

Responsibilities

• Own end-to-end delivery of designs (SOC and Sub-system integration) from timing constraints and timing signoff perspective.
• Work closely with the SOC Architecture team for SOC clocks & STA for statistical timing target goals.
• Understanding clock design requirements and making sure they are correctly set up in SDC.
• Understand timing margins (LVF/SSTA/Variations etc.) on the latest tech nodes and work with timing methodology teams for future and current projects.
• Understand design requirements, timelines and various milestones of a project and deliver FCT closure accordingly.
• Collaborate with CAD and EDA vendors to strengthen AMD timing closure and constraints methodology.
• Responsible for cdc/lint, timing closure, lower power implementation and netlist quality check with RTL designer and PD team.
• Work on SDC development, STA (Static Timing) analysis, shift left of timing closure, CDC (Clock Domain Crossing).

Skills

STA

Constraints

Timing Signoff

Physical Design

SNPS PT/GCA

ICC2/FC

MBIST

Clock Implementation

Place & Route

CTS

Verilog RTL

Perl/TCL

Python

Digital ASIC

Synthesis

Low Power

English

Education

Bachelor/Master’s degree in Micro Electronics/Integrated Circuit Science

Tools

SNPS PT/GCA

ICC2/FC

Job description

Advanced Micro Devices in Santa Clara, CA is seeking a STA/Constraints Engineer to develop full-chip constraints and drive timing closure. You’ll collaborate with Fellows, Principal Engineers, Architects, and cross-functional teams across Physical Design, Timing Analysis, Synthesis, and Power signoff to deliver reliable FCT closure.

The role requires deep experience in STA, constraints, DFT timing concepts, and proficient scripting with Perl/TCL/Python.