Senior SoC Verification Engineer - UVM, PCIe & Ethernet

Yochana; United States; On-site; USD 120,000 - 160,000; Full time

Job summary

Yochana is seeking a senior ASIC verification engineer to own block-level verification across multiple complex designs. The role requires end-to-end UVM experience from scratch and hands-on work with high-speed protocols.

You will develop testbenches, sequences, agents, and coverage models in SystemVerilog, perform waveform analysis, and collaborate with customer teams to align verification with top-level testbenches.

Qualifications

• End-to-end UVM experience from scratch.
• 6 to 10+ years of ASIC verification in complex designs.
• Expert in SystemVerilog and UVM; testbenches and components built from scratch.
• Hands-on verification with high-speed protocols including Ethernet.
• Experience debugging with industry simulators and waveform analysis.

Responsibilities

• Own block-level verification of 4-5 complex design blocks per project.
• Develop and maintain verification components, sequences, agents, scoreboards, and coverage models from scratch in SystemVerilog/UVM.
• Execute directed and constrained-random tests; drive functional and code coverage closure.
• Apply knowledge of UCIe 2.0, PCIe, and Ethernet to verify architectural features.
• Collaborate with customer engineering teams and internal leads to align with top-level testbench.
• Perform waveform analysis, protocol debugging, root-cause analysis, and regression triage.

Skills

End-to-end ASIC verification

SystemVerilog

UVM

From scratch testbench development

Waveform analysis

Tools

Synopsys VCS

Cadence Xcelium

Mentor Questa

Job description

Yochana is seeking a senior ASIC verification engineer to own block-level verification across multiple complex designs. The role requires end-to-end UVM experience from scratch and hands-on work with high-speed protocols.

You will develop testbenches, sequences, agents, and coverage models in SystemVerilog, perform waveform analysis, and collaborate with customer teams to align verification with top-level testbenches.