Senior SoC Verification Engineer: End-to-End UVM from Scratch

CBL Solutions; United States; On-site; USD 120,000 - 180,000; Full time

Job summary

CBL Solutions in the United States seeks an experienced ASIC verification engineer to own end-to-end verification for multiple blocks, building testbenches and components from scratch using SystemVerilog and UVM.

You will apply deep protocol knowledge (UCIe 2.0, PCIe, Ethernet) to verify architectural features, execute directed and constrained-random tests, and collaborate with customer teams to align verification with the top-level testbench infrastructure.

Qualifications

• 6 to 10+ years of ASIC verification experience in complex digital designs.
• Expert-level proficiency in SystemVerilog and UVM, with testbenches and components built from scratch.
• Hands-on verification experience with high-speed protocols: Ethernet, PCIe, UCIe 2.0.

Responsibilities

• Block-Level Verification Ownership: own verification of 4-5 complex design blocks per project.
• Testbench & Component Development: build and maintain verification components, sequences, agents, scoreboards, and coverage models from scratch.
• Verification Execution: run directed and constrained-random tests, debug failures, drive functional and coverage closure.
• Protocol Application: apply deep knowledge of protocols (UCIe 2.0, PCIe, Ethernet) to verify architectural features.
• Collaboration: interface with customer engineering teams and internal leads to align with top-level testbench infrastructure.
• Debugging & Triage: perform waveform analysis, protocol debugging, root-cause analysis, and regression triage using industry simulators.

Skills

SystemVerilog

UVM

Testbench Development

Constrained-Random Testing

Debugging

Ethernet

Tools

Synopsys VCS

Cadence Xcelium

Mentor Questa

Job description

CBL Solutions in the United States seeks an experienced ASIC verification engineer to own end-to-end verification for multiple blocks, building testbenches and components from scratch using SystemVerilog and UVM.

You will apply deep protocol knowledge (UCIe 2.0, PCIe, Ethernet) to verify architectural features, execute directed and constrained-random tests, and collaborate with customer teams to align verification with the top-level testbench infrastructure.