SOC Verification Engineers

Mirafra; San Jose (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

A leading technology company in California is looking for an experienced professional to handle ASIC design verification for various processing blocks within a System on Chip (SoC). Candidates should hold a B.S. or M.S. degree in Computer Engineering or related field and possess over 8 years of experience in ASIC verification. Strong expertise in System Verilog and UVM methodology is essential for this role. This opportunity offers a chance to work on advanced projects in a dynamic environment.

Qualifications

• 8+ years of experience in ASIC verification.
• Strong knowledge of System Verilog and UVM methodology.

Responsibilities

• Responsible for ASIC design verification for various processing blocks within a SOC.
• Develop and complete test plans for cache coherency verification of ASIC-based SoCs using UVM-based environments.
• Design and implement constrained-random and directed System Verilog testbenches targeting multi-level cache hierarchies.

Skills

System Verilog

UVM methodology

ASIC verification

Education

B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or related field

Job description

Responsible for ASIC design verification for various processing blocks within a SOC

• Develop and complete test plans for cache coherency verification of ASIC-based SoCs using UVM-based environments.
• Design and implement constrained-random and directed System Verilog testbenches targeting multi-level cache hierarchies

What we need to see:

• B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent experience).
• 8+ years of experience in ASIC verification,
• Strong knowledge of System Verilog and UVM methodology.