Lead SoC Design Verification Architect

Veriipro; Santa Clara (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

Veriipro in Santa Clara, California is looking for a Principal Design Verification Engineer to oversee verification activities for complex SoC designs. The successful candidate will architect advanced verification environments and create test plans while collaborating with cross-functional teams to ensure quality silicon delivery.

You will lead verification efforts, develop automation tools, and mentor junior engineers in a fast-paced environment. Required qualifications include a Bachelor's degree and substantial experience in design verification.

Qualifications

• 10+ years of design verification experience; or a Master's/Ph.D. with 5+ years of relevant experience.
• Proficiency with Python or Perl scripting.
• Strong understanding of object-oriented programming concepts.

Responsibilities

• Lead design verification for complex SoC and ASIC projects.
• Develop verification architectures and test plans.
• Debug design failures and work closely with design engineers.

Skills

Design Verification

UVM-based environments

Automation tools

Python scripting

SystemVerilog

C++ programming

Education

Bachelor's degree in relevant fields

Tools

EDA verification tools

Job description

Veriipro in Santa Clara, California is looking for a Principal Design Verification Engineer to oversee verification activities for complex SoC designs. The successful candidate will architect advanced verification environments and create test plans while collaborating with cross-functional teams to ensure quality silicon delivery.

You will lead verification efforts, develop automation tools, and mentor junior engineers in a fast-paced environment. Required qualifications include a Bachelor's degree and substantial experience in design verification.