Senior SoC Power & RTL Optimization Engineer

MatX; Mountain View (CA); On-site; USD 150,000 - 450,000; Full time

Benefits offered by this job

Health, Dental, Vision & Life保险

HSA with company contribution

4 weeks PTO + 12 holidays + 3 weeks of

Remote/flexible work per year

Professional development $1,500/year

Team lunches and off-sites

Job summary

MatX is building a silicon-focused platform for AGI workloads in Mountain View. We are hiring silicon micro-architects and design engineers to deliver high-perf, power-efficient silicon for compute, memory management, and interconnect across AI accelerators.

The team will develop power estimation methodologies, build energy models, perform RTL and gate-level power analysis, and collaborate with architects to optimize microarchitecture and RTL for power efficiency.

Qualifications

• Develop power estimation methodologies for AI accelerator SoCs.
• Build and calibrate energy models for architectural exploration and power target definition.
• Perform RTL, gate-level, and post-layout power analysis across SoC subsystems.
• Analyze AI workloads to identify opportunities for power reduction.
• Drive power optimization across compute, memory, interconnect, PCIe, HBM and related subsystems.
• Collaborate with architects and RTL designers on power-efficient microarchitecture.

Responsibilities

• Develop power estimation methodologies for AI accelerator SoCs.
• Build and calibrate energy models for architectural exploration and power target definition.
• Perform RTL, gate-level, and post-layout power analysis across major SoC subsystems.
• Analyze AI workloads and applications for power reduction opportunities.
• Drive power optimization across compute, memory, interconnect, PCIe, HBM, clock/reset, and other subsystems.
• Collaborate with architects and RTL designers to implement power-efficient microarchitecture and RTL improvements.
• Work with physical design teams to evaluate power trade-offs.
• Define workloads and sign-off scenarios to improve power analysis coverage.
• Develop automation, scripts, dashboards, and heuristics to accelerate power analysis.
• Present results and design recommendations to cross-functional teams.

Skills

Power estimation

Energy modeling

RTL power analysis

Power optimization

Work independence

Cross-functional collaboration

Python/Perl scripting

Education

BS or MS in Electrical/Computer Engineering

Tools

Python

Perl

Job description

MatX is building a silicon-focused platform for AGI workloads in Mountain View. We are hiring silicon micro-architects and design engineers to deliver high-perf, power-efficient silicon for compute, memory management, and interconnect across AI accelerators.

The team will develop power estimation methodologies, build energy models, perform RTL and gate-level power analysis, and collaborate with architects to optimize microarchitecture and RTL for power efficiency.