Hybrid SOC Micro-Architect & RTL Design Engineer

MatX; Mountain View (WY); On-site; USD 120,000 - 600,000; Full time

Benefits offered by this job

Equity

Health insurance

Paid time off

Parental leave

Professional development

401K

Remote work options

Commute reimbursement

MatX Extras

Job summary

MatX is building a silicon-focused compute platform for AGI and is hiring silicon micro-architects and design engineers to create high-performance, sustainable GenAI silicon. You will drive architecture-to-design flows for subsystems and full chips, owning milestones from micro-architecture to tapeout.

Collaboration with verification, DFT, and physical design teams is essential to achieve optimal power, performance, and area.

Qualifications

• Concept-to-silicon experience driving silicon design from architecture to production
• SystemVerilog, Python, C/C++ experience for chip design
• Production-proven silicon micro-architecture and design concepts
• Experience testing designs and working with verification teams
• Design synthesis, equivalence checking, lint, clock-domain-crossing
• DFT and physical design concepts for high test coverage
• Familiarity with verification/emulation platforms a plus
• Experience in silicon bring-up a plus

Responsibilities

• Contribute to silicon architecture-to-design methodology with scalable solutions across blocks, subsystems, fullchip design
• Own subsystem or chip-level deliverables from micro-architecture to sign-off ready design
• Plan and drive reviews on micro-architecture, design specs, execution progress, and timing closure toward milestones including tapeout
• Collaborate with verification, DFT, and physical design co-owners to achieve best-in-class performance-power-area results

Job description

MatX is building a silicon-focused compute platform for AGI and is hiring silicon micro-architects and design engineers to create high-performance, sustainable GenAI silicon. You will drive architecture-to-design flows for subsystems and full chips, owning milestones from micro-architecture to tapeout.

Collaboration with verification, DFT, and physical design teams is essential to achieve optimal power, performance, and area.