SOC Integration Architect for High-Performance SoCs

MatX; Mountain View (CA); On-site; USD 160,000 - 600,000; Full time

Benefits offered by this job

4 weeks PTO (accrued)

12 company holidays

Up to 3 weeks remote work

Health insurance (employee & dependes)

401K with company contributions

Life insurance (employee)

Mental health benefits

Professional development budget

Team meals onsite

Commuting reimbursement

Job summary

MatX in Mountain View, CA, is building a compute platform for AGI and seeks silicon micro-architects and design engineers to deliver high-performance, power-conscious SOC RTL and full-chip integration.

You will partner with design teams to enable top-level RTL, define timing, automation, and support packaging. This full-time role requires SystemVerilog expertise and experience with CPUs/GPUs and high-speed interconnects.

Qualifications

• Proficiency in SystemVerilog and scripting languages (Python/Perl).
• Experience integrating CPUs/GPUs/accelerators with high-speed interconnects (UCIE).
• Knowledge of SOC-level verification and floorplanning in RTL.
• Experience generating memory wrappers and DFT wrappers for Subsystems.

Responsibilities

• Evolve silicon architecture-to-design methodology for full-chip SOC RTL design.
• Collaborate with Design team for System-On-Chip top-level RTL development.
• Automate SOC top-level RTL integration and on-the-fly generation processes.
• Coordinate with Physical Design to align RTL with floorplan connectivity.
• Establish robust clock/reset methodologies across teams.
• Define and validate SoC timing constraints against subsystem and physical design.

Skills

SystemVerilog

Python

Perl

Chip design RTL

CPU/GPU integration

High-speed interconnects

Memory management

Automation scripting

Tools

RTL design tools

Emulation platforms

Verification tools

Job description

MatX in Mountain View, CA, is building a compute platform for AGI and seeks silicon micro-architects and design engineers to deliver high-performance, power-conscious SOC RTL and full-chip integration.

You will partner with design teams to enable top-level RTL, define timing, automation, and support packaging. This full-time role requires SystemVerilog expertise and experience with CPUs/GPUs and high-speed interconnects.