Hybrid Silicon Architect & RTL Designer for AGI Compute

MatX Inc.; Mountain View (CA); Hybrid; USD 160,000 - 600,000; Full time

Benefits offered by this job

4 weeks PTO

Up to 3 weeks remote work

Health insurance

401(k) plan

Relocation support

Job summary

MatX Inc. is building the silicon architecture and design for AGI-grade compute platforms.

We are hiring silicon micro-architects and design engineers to deliver high-performance, power-efficient silicon across CPU/GPU-like blocks and memory systems. You will own subsystem design deliverables from micro-architecture to sign-off, drive reviews, and work with verification and physical design teams to achieve strong performance, timing, and area results.

Qualifications

• Experience driving silicon design from architecture to production silicon.
• 4+ years in SystemVerilog, Python, and C/C++ for chip design flows.
• Strong background in silicon micro-architecture and high-performance compute.
• Experience testing designs and working with verification for performance/coverage.
• Hands-on with design synthesis and linting to achieve sign-off quality.
• Familiarity with verification/emulation platforms is a plus.
• Experience with high-speed I/O IP is a plus.
• Extensive work with data-moving components (caches, buffers, crossbars).

Responsibilities

• Contribute to silicon architecture-to-design methodology across blocks and subsystems.
• Own subsystem or chip-level silicon design deliverables from micro-architecture to sign-off.
• Plan and drive intermediate and sign-off reviews on micro-architecture and design specs, progress, and timing closure.
• Collaborate with verification, DFT, and physical design teams to optimize performance-power-area.

Skills

SystemVerilog

Python

C/C++

Micro-architecture

Verification

Design synthesis

DFT

Emulation

High-speed I/O

Tools

Design synthesis tools

Job description

MatX Inc. is building the silicon architecture and design for AGI-grade compute platforms.

We are hiring silicon micro-architects and design engineers to deliver high-performance, power-efficient silicon across CPU/GPU-like blocks and memory systems. You will own subsystem design deliverables from micro-architecture to sign-off, drive reviews, and work with verification and physical design teams to achieve strong performance, timing, and area results.