Senior SoC Power Optimization Engineer - Hybrid

MatX; Mountain View (WY); Hybrid; USD 120,000 - 475,000; Full time

Benefits offered by this job

Equity options

Health insurance

Paid time off

Parental leave

Professional development

Job summary

MatX is seeking a Senior SoC Power Analysis & Optimization Engineer to lead power estimation for AI accelerators. Hybrid role in Mountain View, CA, focusing on energy models, RTL and post-layout analyses, and power optimizations across SoC subsystems.

Requires 8+ years in high-performance design and strong scripting skills. Join MatX to shape power-aware microarchitecture and collaborate with architects, RTL and physical design teams while presenting findings to cross-functional teams.

Qualifications

• BS or MS in Electrical Engineering, Computer Engineering, or related field.
• 8+ years of experience in SoC, AI accelerator, GPU, networking ASIC, or high-performance digital design.
• Experience with ASIC low-power design techniques.
• Experience performing RTL and gate-level power analysis.
• Strong analytical and debugging skills.
• Experience with Python, Perl, or similar scripting languages.
• Ability to work independently in a fast-paced environment.
• Excellent communication and cross-functional collaboration skills.

Responsibilities

• Develop and maintain power estimation methodologies for AI accelerator SoCs.
• Build and calibrate energy models for architectural exploration and power target definition.
• Perform RTL, gate-level, and post-layout power analysis across major SoC subsystems.
• Analyze AI workloads to identify opportunities for dynamic and static power reduction.
• Drive power optimization across compute, memory, interconnect, PCIe, HBM, clock/reset.

Skills

Power analysis

RTL analysis

Python scripting

Cross-functional collaboration

Analytical debugging

Independent work

Education

BS/MS in Electrical/Computer Engineering

Tools

Power analysis tools

Job description

MatX is seeking a Senior SoC Power Analysis & Optimization Engineer to lead power estimation for AI accelerators. Hybrid role in Mountain View, CA, focusing on energy models, RTL and post-layout analyses, and power optimizations across SoC subsystems.

Requires 8+ years in high-performance design and strong scripting skills. Join MatX to shape power-aware microarchitecture and collaborate with architects, RTL and physical design teams while presenting findings to cross-functional teams.