Senior SOC Physical Verification & Integration Lead

EnCharge AI, Inc.; United States; Remote; USD 180,000 - 300,000; Full time

Job summary

EnCharge AI is seeking a seasoned SOC Physical Verification & Integration Specialist to lead the full-chip physical assembly from floorplan to tapeout, ensuring robust PPA for large SOCs such as AI accelerators.

You will own hierarchical PV flows, drive DRC/LVS/antenna signoffs, and collaborate with PD and STA teams to resolve integration conflicts while working with foundry partners on rule interpretation. Cadence Innovus and Calibre experience is essential.

Qualifications

• 14+ years of hands-on experience in SOC physical design and physical verification.
• Experience taping out very large, complex SOCs such as Datacenter/AI accelerators/HPC.
• Deep understanding of RTL-to-GDSII flow and physical integration challenges.

Responsibilities

• Drive full-chip physical integration of very large-scale SOCs, including floorplanning, bump planning, PG integration, and top-level clock/routing.
• Architect and deploy hierarchical PV flows with clear boundary conditions and interface rules.
• Own full-chip DRC, LVS, ERC, Antenna, ESD, and Latch-up signoff using industry tools (e.g., Calibre) at 5nm/3nm or below.
• Partner with Physical Design and STA teams to resolve integration conflicts and ensure timing closure.
• Collaborate with foundry partners for design-rule interpretation and edge-case reticle-limit violations.
• Develop automation scripts to streamline physical integration tasks and tapeout flows.

Skills

SOC physical design

Physical verification

RTL-to-GDSII flow

Static Timing Analysis (STA)

Scripting (Tcl/Python/Perl)

Education

Bachelor’s or Master’s degree in Electrical/Computer Engineering

Tools

Cadence Innovus

Calibre (nmDRC/nLVS/PERC)

Synopsys IC Validator

Chip/package co-design tools

Bump planning tools

Job description

EnCharge AI is seeking a seasoned SOC Physical Verification & Integration Specialist to lead the full-chip physical assembly from floorplan to tapeout, ensuring robust PPA for large SOCs such as AI accelerators.

You will own hierarchical PV flows, drive DRC/LVS/antenna signoffs, and collaborate with PD and STA teams to resolve integration conflicts while working with foundry partners on rule interpretation. Cadence Innovus and Calibre experience is essential.