Principal SOC Physical Verification & Integration Specialist

EnCharge AI, Inc.; United States; Remoto; USD 180.000 - 300.000; Tempo pieno

Descrizione del lavoro

EnCharge AI is seeking a seasoned SOC Physical Verification & Integration Specialist to lead the full-chip physical assembly from floorplan to tapeout, ensuring robust PPA for large SOCs such as AI accelerators.

You will own hierarchical PV flows, drive DRC/LVS/antenna signoffs, and collaborate with PD and STA teams to resolve integration conflicts while working with foundry partners on rule interpretation. Cadence Innovus and Calibre experience is essential.

Competenze

• 14+ years of hands-on experience in SOC physical design and physical verification.
• Experience taping out very large, complex SOCs such as Datacenter/AI accelerators/HPC.
• Deep understanding of RTL-to-GDSII flow and physical integration challenges.

Mansioni

• Drive full-chip physical integration of very large-scale SOCs, including floorplanning, bump planning, PG integration, and top-level clock/routing.
• Architect and deploy hierarchical PV flows with clear boundary conditions and interface rules.
• Own full-chip DRC, LVS, ERC, Antenna, ESD, and Latch-up signoff using industry tools (e.g., Calibre) at 5nm/3nm or below.
• Partner with Physical Design and STA teams to resolve integration conflicts and ensure timing closure.
• Collaborate with foundry partners for design-rule interpretation and edge-case reticle-limit violations.
• Develop automation scripts to streamline physical integration tasks and tapeout flows.

Conoscenze

SOC physical design

Physical verification

RTL-to-GDSII flow

Static Timing Analysis (STA)

Scripting (Tcl/Python/Perl)

Formazione

Bachelor’s or Master’s degree in Electrical/Computer Engineering

Strumenti

Cadence Innovus

Calibre (nmDRC/nLVS/PERC)

Synopsys IC Validator

Chip/package co-design tools

Bump planning tools

Descrizione del lavoro

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

The Role

We are seeking a thorough SOC Physical Verification & Integration Specialist to drive the physical assembly and signoff of our next-generation SOCs. In this role, you will own the physical integration strategy from the floorplan stage through to tapeout, ensuring seamless assembly of massive multi-hierarchical blocks. You will act as the critical bridge between block-level implementation, top-level integration, and final foundry signoff, ensuring that complex physical bottlenecks are resolved without compromising power, performance, or area (PPA).

Key Responsibilities

• Top-Level Physical Integration: Drive the full-chip physical assembly of very large-scale SOCs (e.g., multi-billion transistor designs). Manage top-level floorplanning, bump planning, global power grid (PG) integration, and top-level clock/routing integration.
• Hierarchical Verification Methodology: Architect and deploy highly efficient, hierarchical physical verification (PV) flows. Define the boundary conditions, abstraction models, and interface rules required to assemble heavily partitioned, massive-scale designs.
• Signoff Execution & Debugging: Own full-chip DRC, LVS, ERC, Antenna, ESD, and Latch-up signoff using industry-standard tools (e.g., Siemens Calibre) at advanced process nodes (5nm, 3nm, or below).
• Cross-Functional Collaboration: Partner tightly with the Physical Design (PD) and Static Timing Analysis (STA) teams. Proactively resolve integration conflicts—such as top-level routing congestion or interface timing violations—ensuring that physical fixes do not disrupt timing closure.
• Design Rule Co-Optimization: Work directly with foundry partners to interpret complex design rules and waive or resolve edge-case violations specific to reticle-limit designs.
• Automation & Flow Development: Develop robust scripts and utilities to automate physical integration tasks, database merging, and PV result parsing to accelerate the tapeout cycle.

Required Qualifications

Experience: 14 + years of hands-on experience in SOC physical design and physical verification, with a proven track record of taping out very large, complex SOCs (e.g., Datacenter, AI accelerators, or High-Performance Compute chips).

Technical Domain Expertise : * Deep understanding of the entire RTL-to-GDSII flow, with expert-level knowledge of physical integration challenges in flat vs. hierarchical methodologies.

• Strong foundational understanding of Physical Design and Static Timing Analysis (STA) to effectively communicate with implementation teams and assess the timing impact of PV fixes.

Tool Proficiency: * Mastery of top-level integration tools (Cadence Innovus).

• Expertise in physical verification suites (e.g., Siemens Calibre nmDRC/nLVS/PERC, Synopsys IC Validator).

• Familiarity with chip/package co-design and bump planning tools.

Programming/Scripting: High proficiency in Tcl, Python, and/or Perl for EDA flow automation and database manipulation.

• Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

Preferred Qualifications

• Experience with multi-die integration, 2.5D/3D packaging, or chiplet-based architectures.
• Previous experience leading tapeout operations for start-up or fast-paced advanced technology environments.
• Advanced knowledge of custom layout integration and mixed-signal IP drop-in