SoC Physical Verification Engineer: AI‑Driven Flows

Micron Technology; Richardson (TX); On-site; USD 97,000 - 205,000; Full time

Job summary

Micron Technology is seeking a Physical Verification Engineer to lead full-chip PV sign-off for 3nm-scale memory and heterogeneous integration die. You will collaborate with design, EDA, and foundry teams, driving verification quality and sign-off readiness from layout through silicon.

The role emphasizes DRC/LVS/ERC/PERC, rule deck development, ML/AI-driven PV tools, and tight coordination across global teams to meet ambitious tape-out schedules.

Qualifications

• Experience with full-chip or block-level physical verification for advanced-node SoCs or memory designs.
• Experience in physical verification methodologies including DRC, LVS, ERC, PERC, DFM, antenna, and reliability sign-off.
• Familiarity with industry PVS tools and rule deck development.

Responsibilities

• Implement physical verification sign-off for full-chip designs including DRC, LVS, ERC, PERC, antenna checks, and DFM.
• Develop and debug foundry rule decks and manage waivers for advanced nodes.
• Perform RC extraction and correlate PV results with post-silicon measurements.
• Develop PV flows, automation, and regression infrastructure using scripting languages.
• Drive AI-enabled PV workflows and collaborate with cross-functional teams from design to foundry.

Skills

Physical verification

DRC/LVS/ERC

Python scripting

AI in PV

Cross-functional teamwork

Education

Master's or PhD in Electrical/Computer Engineering

Tools

Calibre

IC Validator (ICV)

Pegasus

Job description

Micron Technology is seeking a Physical Verification Engineer to lead full-chip PV sign-off for 3nm-scale memory and heterogeneous integration die. You will collaborate with design, EDA, and foundry teams, driving verification quality and sign-off readiness from layout through silicon.

The role emphasizes DRC/LVS/ERC/PERC, rule deck development, ML/AI-driven PV tools, and tight coordination across global teams to meet ambitious tape-out schedules.