Senior SoC Physical Design Lead (RTL-to-GDSII)

NXP Semiconductors NV; Austin (TX); On-site; USD 140,000 - 230,000; Full time

Job summary

NXP Semiconductors NV in Austin, TX seeks an experienced Digital Designer for SoC implementation and physical design. You will own end-to-end PD execution from RTL to silicon for advanced technology nodes and drive delivery to meet PPA targets.

The role emphasizes leadership, cross-functional collaboration with RTL, verification, and architecture teams, plus adoption of advanced node tech and automation. Strong ASIC/SoC PD background and Cadence/Synopsys tool proficiency are essential.

Qualifications

• Bachelor’s or Master’s in Electrical / Electronics Engineering or related field.
• 10+ years of ASIC/SoC physical design experience.
• Strong knowledge of industry EDA tools (Synopsys, Cadence flows).
• Strong communication skills.

Responsibilities

• Lead Physical design execution including floorplanning, synthesis, place & route, CTS, routing, STA, PDN, PDV and signoff.
• Drive timing, power, IR/EM, and physical verification closure to achieve tapeout readiness.
• Deliver optimized PPA across complex designs.
• Aligns with internal expectations of implementing designs on silicon with optimal quality, PPA, and cost efficiency

Skills

Strong communication skills

Education

Bachelor’s or Master’s in Electrical / Electronics Engineering or related field

Tools

Cadence flows

Synopsys flows

Python

TCL

Perl

Job description

NXP Semiconductors NV in Austin, TX seeks an experienced Digital Designer for SoC implementation and physical design. You will own end-to-end PD execution from RTL to silicon for advanced technology nodes and drive delivery to meet PPA targets.

The role emphasizes leadership, cross-functional collaboration with RTL, verification, and architecture teams, plus adoption of advanced node tech and automation. Strong ASIC/SoC PD background and Cadence/Synopsys tool proficiency are essential.