Chip Lead & Physical Design Director — Drive SoC PPA

Cadence Design Systems; Austin (TX); On-site; USD 180,000 - 240,000; Full time

Job summary

Cadence Design Systems in Austin, TX is seeking a highly experienced Physical Design Architect/Chip Lead to drive RTL-to-GDS efforts for SoCs in data centers, automotive, and AI domains.

You will lead a PD team, influence sign-off criteria, and collaborate with customers to meet PPAS targets. 15+ years in PD with extensive EDA tool experience, especially Genus, Innovus, and PrimeTime, are expected.

Qualifications

• Have 15+ years in Physical Design or equivalent.
• Bachelor’s in CS/Engineering or related field.
• Strong fundamentals in digital design and semiconductor concepts.
• Experience with IC digital implementation flows and backend EDA tools.
• Proven design-closure experience for chip top-level projects.

Responsibilities

• Lead Physical Design and DFT teams from RTL/Netlist to GDS.
• Drive PPAS optimization and meet aggressive design schedules.
• Guide foundry/node selection and memory/compiler choices.
• Collaborate with Cadence tool R&D to improve methodologies.
• Share best practices and lessons learned across programs.

Skills

Digital Design

Semiconductor fundamentals

RTL-to-GDS flow

Scripting: Tcl/Perl/Python

Customer-facing communication

Education

Bachelor’s degree in CS/Engineering

Master’s degree preferred

Tools

Genus

Innovus

Conformal

Tempus

Modus

Voltus

ICC/ICC2

PrimeTime

Job description

Cadence Design Systems in Austin, TX is seeking a highly experienced Physical Design Architect/Chip Lead to drive RTL-to-GDS efforts for SoCs in data centers, automotive, and AI domains.

You will lead a PD team, influence sign-off criteria, and collaborate with customers to meet PPAS targets. 15+ years in PD with extensive EDA tool experience, especially Genus, Innovus, and PrimeTime, are expected.