Senior Digital Design Engineer: RTL IP & SoC Expert

NXP Semiconductors; Austin (TX); Hybrid; USD 120.000 - 180.000; Vollzeit

Zusammenfassung

NXP Semiconductors in Austin (Oakhill Office) is seeking a Senior Digital Design Engineer to contribute to IP development for DDR, Display Controller, high-speed serial links, cores, memory controllers, and interconnect. The role emphasizes RTL design in Verilog/SystemVerilog, verification collaboration, and documentation for silicon release.

You will work with cross-functional teams from architecture to applications engineering, ensuring quality and on-schedule delivery of IP blocks used across

Qualifikationen

• Bachelor's degree in Electrical/Computer Science or related field.
• Minimum 4 years of IP or SoC design experience.
• Knowledge of SoC architecture required.
• Expert knowledge of Verilog required.
• Experience with quality checks (Lint, CDC analysis, STA).
• Knowledge of ARM AMBA bus standards desired.
• Knowledge of functional safety is a plus.
• Knowledge of CPU or cache architecture is a plus.
• Knowledge of C and scripting (Perl/Python) is a plus.

Aufgaben

• Audit IP architecture specs, plan design and documentation.
• Design IP meeting requirements using RTL (Verilog/SystemVerilog).
• Collaborate with verification team to achieve full coverage.
• Deliver RTL design and supporting docs for silicon.
• Track milestones, defects, and trace requirements to design.

Kenntnisse

Verilog

SystemVerilog

ARM AMBA

SoC architecture

IP design

C programming

Scripting (Perl/Python)

Lint/CDC/STA

Functional safety

Ausbildung

BSEE/BSCE/BSCS

Jobbeschreibung

NXP Semiconductors in Austin (Oakhill Office) is seeking a Senior Digital Design Engineer to contribute to IP development for DDR, Display Controller, high-speed serial links, cores, memory controllers, and interconnect. The role emphasizes RTL design in Verilog/SystemVerilog, verification collaboration, and documentation for silicon release.

You will work with cross-functional teams from architecture to applications engineering, ensuring quality and on-schedule delivery of IP blocks used across