Senior Physical Design Engineer - High-Performance PHY

Apple Inc.; Sunnyvale (CA); On-site; USD 184,700 - 324,800; Full time

Job summary

Apple Inc. in Cupertino, California is seeking a forward‑thinking Physical Design Engineer to contribute to high‑performance PHY design from RTL to GDSII.

You will work with architecture, CAD, timing, and logic teams to deliver outstanding PHY designs that impact millions of Apple customers. Responsibilities include block/chip level constraints, floorplanning, clock network guidelines, place and route, ECOs, and physical verification.

Qualifications

• Bachelors of Science in Electrical Engineering and 10+ years experience preferred.

Responsibilities

• Generate block/chip level static timing constraints.
• Build full chip floor‑plan including pin placement, partitions and power grid.
• Develop and validate high performance low power clock network guidelines.
• Perform block level place and route and close the design to meet timing, area and power constraints.
• Generate and implement ECOs to fix timing, noise and EM IR violations.
• Run physical design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers.
• Assist in flow development for chip integration.

Education

Bachelors of Science in Electrical Engineering

Job description

Apple Inc. in Cupertino, California is seeking a forward‑thinking Physical Design Engineer to contribute to high‑performance PHY design from RTL to GDSII.

You will work with architecture, CAD, timing, and logic teams to deliver outstanding PHY designs that impact millions of Apple customers. Responsibilities include block/chip level constraints, floorplanning, clock network guidelines, place and route, ECOs, and physical verification.