Senior IC Physical Design Engineer - Synthesis to Signoff

Arrow Electronics; San Jose (CA); On-site; USD 87,400 - 165,000; Full time

Job summary

Arrow Electronics is seeking a Physical Design Engineer II to drive ASIC partition implementation, including synthesis, place-and-route, and timing convergence. You will collaborate with architects, RTL designers, and DFT engineers to resolve issues and ensure clean signoffs.

Strong PD flow expertise and TCL scripting are highly valued. The role requires 7+ years in physical design, proficiency with Innovus/Tempus/Quantus, and experience in SoC design and sub-7nm processes.

Qualifications

• Bachelor's degree or equivalent practical experience in a related technical field.
• 7+ years hands-on experience in physical design and implementation (synthesis, PnR, timing convergence, physical verification).
• Proficiency with EDA tools (Innovus, Tempus, Quantus) and strong knowledge of PD flows and methodologies.

Responsibilities

• Execute synthesis, PnR, and STA for assigned ASIC partitions within schedules and goals.
• Collaborate with architects, RTL, and DFT teams to resolve issues across blocks.
• Close EM/IR, drive LEC and physical verification signoff with methodology owners.
• Identify and address physical design challenges, enabling efficient iteration and convergence.

Skills

Physical design

Low-power design techniques

SoC experience

TCL scripting

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Innovus

Tempus

Quantus

Job description

Arrow Electronics is seeking a Physical Design Engineer II to drive ASIC partition implementation, including synthesis, place-and-route, and timing convergence. You will collaborate with architects, RTL designers, and DFT engineers to resolve issues and ensure clean signoffs.

Strong PD flow expertise and TCL scripting are highly valued. The role requires 7+ years in physical design, proficiency with Innovus/Tempus/Quantus, and experience in SoC design and sub-7nm processes.