Senior SoC Layout & Full-Chip Integration Expert

Intel; Hillsboro (OR); On-site; USD 120,000 - 160,000; Full time

Job summary

Intel Foundry’s Design Technology Platform team seeks a senior engineer to lead full-chip floorplanning and keep advanced-node silicon programs on track. You will drive custom layout methodologies, ensure reliable physical verification, and enable tapeout readiness across multi-disciplinary teams.

You will develop automation and design flows using Tcl, Python, and SKILL, while collaborating with PDK and EDA partners to advance FinFET/GAA processes and manufacturability.

Qualifications

• Masters degree in Electrical Engineering, Computer Engineering, or a related field with 4+ years of industry experience. OR a PhD in the same field with 1+ years of industry experience.
• Custom/analog/mixed-signal layout experience in advanced technology nodes.
• Front-end (FEOL) layout rules, transistor-level matching, parasitic layout concepts, and custom silicon structures.
• Debugging skills in physical verification (LVS, DRC, DFM) using Calibre or ICV.
• Tcl, Python, or SKILL to automate layout creation, checking, and full-chip database manipulation.

Responsibilities

• Lead full-chip floorplanning, physical integration, and tapeout activities for advanced-node silicon development vehicles.
• Develop and enhance custom layout methodologies and physical design flows.
• Drive physical verification closure, including DRC, LVS, DFM, density, and antenna rule compliance.
• Collaborate with Technology Development, PDK, and EDA teams to implement scalable and manufacturable design solutions.
• Analyze advanced-node design rules and contribute to design enablement for emerging process technologies, including FinFET and GAA architectures.
• Develop automation solutions using Tcl, Python, SKILL, or similar scripting languages to improve design productivity and quality.
• Coordinate cross-functional activities to ensure tape-in readiness, database integrity, and successful project execution.

Skills

Ownership

Communication

Problem solving

Collaboration

Education

Masters degree in Electrical Engineering or Computer Engineering

PhD in Electrical Engineering or Computer Engineering

Tools

Calibre

ICV

Tcl

Python

SKILL

Job description

Intel Foundry’s Design Technology Platform team seeks a senior engineer to lead full-chip floorplanning and keep advanced-node silicon programs on track. You will drive custom layout methodologies, ensure reliable physical verification, and enable tapeout readiness across multi-disciplinary teams.

You will develop automation and design flows using Tcl, Python, and SKILL, while collaborating with PDK and EDA partners to advance FinFET/GAA processes and manufacturability.