Senior SoC Physical Layout & Full-Chip Integration Engineer

Intel Corporation; Hillsboro (OR); On-site; USD 122,000 - 232,000; Full time

Job summary

Intel Corporation's Design Technology Platform (DTP) in Intel Foundry seeks engineers to lead full-chip floorplanning, physical integration, and tapeout for advanced-node silicon development vehicles in Hillsboro, Oregon and other sites.

You will develop custom layout methodologies, drive physical verification closure (LVS/DRC/DFM), and collaborate with PDK and EDA teams to deliver scalable design flows for FinFET and GAA architectures.

Qualifications

• Masters in Electrical Engineering, Computer Engineering or related field with 4+ years industry experience.
• OR a PhD in the same field with 1+ years industry experience.
• Custom/analog/mixed-signal layout design experience in advanced technology nodes.
• Front-end (FEOL) layout design rules, transistor-level matching, parasitic layout concepts, and custom silicon structures.
• Debugging skills in physical verification (LVS, DRC, and DFM) using industry-standard verification engines (Calibre/ICV).
• Scripting with Tcl, Python, or SKILL to automate layout creation, checking, and full-chip database manipulation.

Responsibilities

• Lead full-chip floorplanning, physical integration, and tapeout activities for advanced-node silicon development vehicles.
• Develop and enhance custom layout methodologies and physical design flows.
• Drive physical verification closure, including DRC, LVS, DFM, density, and antenna rule compliance.
• Collaborate with Technology Development, PDK, and EDA teams to implement scalable and manufacturable design solutions.
• Analyze advanced-node design rules and contribute to design enablement for FinFET and Gate-All-Around architectures.
• Develop automation solutions using Tcl, Python, SKILL to improve design productivity and quality.
• Coordinate cross-functional activities to ensure tape-in readiness, database integrity, and successful project execution.

Skills

Tcl/Python/SKILL scripting

Education

Masters in Electrical/Computer Engineering or related field

PhD in Electrical/Computer Engineering or related field

Tools

Calibre/ICV

Cadence Virtuoso

Job description

About the Role

Join the Design Technology Platform (DTP) organization within Intel Foundry and help drive the development of the methodologies, physical layouts, and silicon platforms that enable next-generation semiconductor technologies. As a member of the X-Chip Full-Chip Integration team, you will play a key role in developing custom layout methodologies, leading full-chip physical integration, and driving physical verification and tapeout execution for advanced testchip and silicon lead vehicles on cutting-edge process technologies. This role is ideal for engineers who have a passion for custom layout design, advanced-node physical design methodologies, and solving complex physical integration challenges. You will work at the intersection of technology development, physical design, verification, and manufacturing, collaborating with experts across Intel Foundry to enable future process technologies and silicon solutions.

What You'll Do

• Lead full-chip floorplanning, physical integration, and tapeout activities for advanced-node silicon development vehicles.
• Develop and enhance custom layout methodologies and physical design flows.
• Drive physical verification closure, including DRC, LVS, DFM, density, and antenna rule compliance.
• Collaborate with Technology Development, PDK, and EDA teams to implement scalable and manufacturable design solutions.
• Analyze advanced-node design rules and contribute to design enablement for emerging process technologies, including FinFET and Gate-All-Around (GAA) architectures.
• Develop automation solutions using Tcl, Python, SKILL, or similar scripting languages to improve design productivity and quality.
• Coordinate cross-functional activities to ensure tape-in readiness, database integrity, and successful project execution.

Why Join Intel Foundry?

At Intel Foundry, you'll have the opportunity to influence the future of semiconductor technology by helping develop the methodologies and silicon platforms that enable next-generation manufacturing processes. In this role, you will: Work on some of the industry's most advanced semiconductor technologies and process nodes. Collaborate with world-class experts across design, process technology, manufacturing, yield engineering, and EDA development. Drive highly visible projects that directly impact technology readiness and future product development. Gain exposure across the full silicon lifecycle, from concept and methodology development through tape-in and silicon validation. Expand your technical leadership while solving challenging engineering problems at global scale. Benefit from Intel's commitment to innovation, career development, and comprehensive employee benefits. See Intel Benefits for more details.

Minimum Qualifications and Experience

• Masters' degree in Electrical Engineering, Computer Engineering, or a related field with 4+ years of industry experience.
• OR a PhD’s degree in the same filed with 1+ years of industry experience.
• Custom/analog/mixed-signal layout design experience in advanced technology nodes.
• Front-end (FEOL) layout design rules, transistor-level matching, parasitic layout concepts, and custom silicon structures..
• Debugging skills in physical verification (LVS, DRC, and DFM) using industry-standard verification engines (such as Calibre or ICV), with a proven ability to solve complex, systemic layout errors.
• Tcl, Python, or SKILL to automate layout creation, checking, and full-chip database manipulation.

Preferred Qualifications and Experience

• Experience with top-level floorplanning, RDL/bump planning, or backside power delivery (PowerVia) implementation.
• Proven track record of collaborating with PDK and Technology Development teams on design rule definitions, test structure vehicles, or DRC suppression strategies.
• Experience managing physical tapeout schedules, IP tracking matrices, and formal physical design Quality Assurance (QA) flows.
• Familiarity with custom layout environments (such as Cadence Virtuoso) and translating custom databases into full-chip NDM flows.
• Previous related work experience in a semiconductor foundry preferred.

Location

Primary – Hillsboro OR Additional – Chandler AZ, Austin TX.

Job Type

Experienced Hire Shift: Shift 1 (United States of America)

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD

Position of Trust

Position of Trust N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.