Hardware / Lab Technician - Layout Design Engineer

Trinus Corporation; Santa Clara (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Trinus Corporation is seeking a senior IC layout engineer with 10+ years of custom IC layout experience, including memory IP. You will contribute to SRAM design, memory compiler efforts, and advanced CMOS node initiatives.

Candidates will master Cadence Virtuoso, perform DRC/LVS debugging, and collaborate with circuit, physical, CAD, and foundry teams. Strong communication and mentorship skills are essential; knowledge of layout automation or AI tools is a plus.

Qualifications

• 10+ years of custom IC layout experience, including 5+ years in SRAM, memory IP layout.
• Hands-on participation in advanced CMOS technology initiatives, preferably focusing on FinFET or GAA nodes at 5nm, 3nm, or smaller.
• Solid grasp of SRAM and memory layout principles.
• Extensive experience with Cadence Virtuoso for custom layout creation and assessment.
• Extensive experience with DRC/LVS debugging using Calibre, ICV, or similar physical verification tools.
• Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.
• Direct familiarity with advanced-node layout limitations and layout-dependent phenomena (LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar).
• Ability to work with circuit build, physical build, integration, CAD, and foundry teams.
• Clear communication, ownership, good judgment, and ability to mentor other engineers.
• Knowledge of layout automation or AI tools is a definite plus.

Skills

IC layout

CMOS technology

Memory IP layout

Mentoring engineers

Communication

Tools

Cadence Virtuoso

Calibre

ICV

Job description

• 10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.
• Hands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions.
• Solid grasp of SRAM and memory layout principles.
• Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment.
• Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools.
• Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.
• Direct familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise.
• Ability to work effectively with circuit build, physical build, integration, CAD, and foundry teams.
• Clear communication, strong ownership, good judgment, and the ability to mentor other engineers.
• Knowledge of layout automation or AI tools is a definite plus.