Senior SoC Layout Engineer: Full-Chip Integration (Hybrid)

Intel Corporation; Hillsboro (OR); On-site; USD 122,000 - 232,000; Full time

Job summary

Intel Corporation's Design Technology Platform (DTP) in Intel Foundry seeks engineers to lead full-chip floorplanning, physical integration, and tapeout for advanced-node silicon development vehicles in Hillsboro, Oregon and other sites.

You will develop custom layout methodologies, drive physical verification closure (LVS/DRC/DFM), and collaborate with PDK and EDA teams to deliver scalable design flows for FinFET and GAA architectures.

Qualifications

• Masters in Electrical Engineering, Computer Engineering or related field with 4+ years industry experience.
• OR a PhD in the same field with 1+ years industry experience.
• Custom/analog/mixed-signal layout design experience in advanced technology nodes.
• Front-end (FEOL) layout design rules, transistor-level matching, parasitic layout concepts, and custom silicon structures.
• Debugging skills in physical verification (LVS, DRC, and DFM) using industry-standard verification engines (Calibre/ICV).
• Scripting with Tcl, Python, or SKILL to automate layout creation, checking, and full-chip database manipulation.

Responsibilities

• Lead full-chip floorplanning, physical integration, and tapeout activities for advanced-node silicon development vehicles.
• Develop and enhance custom layout methodologies and physical design flows.
• Drive physical verification closure, including DRC, LVS, DFM, density, and antenna rule compliance.
• Collaborate with Technology Development, PDK, and EDA teams to implement scalable and manufacturable design solutions.
• Analyze advanced-node design rules and contribute to design enablement for FinFET and Gate-All-Around architectures.
• Develop automation solutions using Tcl, Python, SKILL to improve design productivity and quality.
• Coordinate cross-functional activities to ensure tape-in readiness, database integrity, and successful project execution.

Skills

Tcl/Python/SKILL scripting

Education

Masters in Electrical/Computer Engineering or related field

PhD in Electrical/Computer Engineering or related field

Tools

Calibre/ICV

Cadence Virtuoso

Job description

Intel Corporation's Design Technology Platform (DTP) in Intel Foundry seeks engineers to lead full-chip floorplanning, physical integration, and tapeout for advanced-node silicon development vehicles in Hillsboro, Oregon and other sites.

You will develop custom layout methodologies, drive physical verification closure (LVS/DRC/DFM), and collaborate with PDK and EDA teams to deliver scalable design flows for FinFET and GAA architectures.