Senior SoC Physical Layout & Full-Chip Integration Engineer

Intel; Hillsboro (OR); On-site; USD 120,000 - 160,000; Full time

Job summary

Intel Foundry’s Design Technology Platform team seeks a senior engineer to lead full-chip floorplanning and keep advanced-node silicon programs on track. You will drive custom layout methodologies, ensure reliable physical verification, and enable tapeout readiness across multi-disciplinary teams.

You will develop automation and design flows using Tcl, Python, and SKILL, while collaborating with PDK and EDA partners to advance FinFET/GAA processes and manufacturability.

Qualifications

• Masters degree in Electrical Engineering, Computer Engineering, or a related field with 4+ years of industry experience. OR a PhD in the same field with 1+ years of industry experience.
• Custom/analog/mixed-signal layout experience in advanced technology nodes.
• Front-end (FEOL) layout rules, transistor-level matching, parasitic layout concepts, and custom silicon structures.
• Debugging skills in physical verification (LVS, DRC, DFM) using Calibre or ICV.
• Tcl, Python, or SKILL to automate layout creation, checking, and full-chip database manipulation.

Responsibilities

• Lead full-chip floorplanning, physical integration, and tapeout activities for advanced-node silicon development vehicles.
• Develop and enhance custom layout methodologies and physical design flows.
• Drive physical verification closure, including DRC, LVS, DFM, density, and antenna rule compliance.
• Collaborate with Technology Development, PDK, and EDA teams to implement scalable and manufacturable design solutions.
• Analyze advanced-node design rules and contribute to design enablement for emerging process technologies, including FinFET and GAA architectures.
• Develop automation solutions using Tcl, Python, SKILL, or similar scripting languages to improve design productivity and quality.
• Coordinate cross-functional activities to ensure tape-in readiness, database integrity, and successful project execution.

Skills

Ownership

Communication

Problem solving

Collaboration

Education

Masters degree in Electrical Engineering or Computer Engineering

PhD in Electrical Engineering or Computer Engineering

Tools

Calibre

ICV

Tcl

Python

SKILL

Job description

Job Details:

Job Description:

About the Role

Join the Design Technology Platform (DTP) organization within Intel Foundry and help drive the development of the methodologies, physical layouts, and silicon platforms that enable next-generation semiconductor technologies.

As a member of the X-Chip Full-Chip Integration team, you will play a key role in developing custom layout methodologies, leading full-chip physical integration, and driving physical verification and tapeout execution for advanced testchip and silicon lead vehicles on cutting-edge process technologies.

This role is ideal for engineers who have a passion for custom layout design, advanced-node physical design methodologies, and solving complex physical integration challenges. You will work at the intersection of technology development, physical design, verification, and manufacturing, collaborating with experts across Intel Foundry to enable future process technologies and silicon solutions.

What You'll Do

Responsibilities include, but are not limited to:

• Lead full-chip floorplanning, physical integration, and tapeout activities for advanced-node silicon development vehicles.
• Develop and enhance custom layout methodologies and physical design flows.
• Drive physical verification closure, including DRC, LVS, DFM, density, and antenna rule compliance.
• Collaborate with Technology Development, PDK, and EDA teams to implement scalable and manufacturable design solutions.
• Analyze advanced-node design rules and contribute to design enablement for emerging process technologies, including FinFET and Gate-All-Around (GAA) architectures.
• Develop automation solutions using Tcl, Python, SKILL, or similar scripting languages to improve design productivity and quality.
• Coordinate cross-functional activities to ensure tape-in readiness, database integrity, and successful project execution.

Successful Candidates Will Demonstrate

Strong ownership and accountability for delivering high-quality technical results.

Ability to make sound technical decisions with limited information and effectively communicate technical tradeoffs.

Excellent project planning, prioritization, and execution skills.

Strong collaboration and influence across multiple engineering disciplines and organizations.

Effective verbal and written communication skills with both technical and non-technical stakeholders.

Curiosity and enthusiasm for learning emerging semiconductor technologies and methodologies.

Ability to navigate ambiguity and solve complex technical challenges in fast-paced development environments.

Continuous improvement mindset focused on automation, scalability, quality, and engineering efficiency.

Why Join Intel Foundry?

At Intel Foundry, you'll have the opportunity to influence the future of semiconductor technology by helping develop the methodologies and silicon platforms that enable next-generation manufacturing processes.

In this role, you will:

• Work on some of the industry's most advanced semiconductor technologies and process nodes.
• Collaborate with world-class experts across design, process technology, manufacturing, yield engineering, and EDA development.
• Drive highly visible projects that directly impact technology readiness and future product development.
• Gain exposure across the full silicon lifecycle, from concept and methodology development through tape-in and silicon validation.
• Expand your technical leadership while solving challenging engineering problems at global scale.
• Benefit from Intel's commitment to innovation, career development, and comprehensive employee benefits. See Intel Benefits for more details.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications and Experience:

Masters' degree in Electrical Engineering, Computer Engineering, or a related field with 4+ years of industry experience. OR a PhD's degree in the same filed with 1+ years of industry experience.

Your experience outlined above must be in the following:

• Custom/analog/mixed-signal layout design experience in advanced technology nodes.
• Front-end (FEOL) layout design rules, transistor-level matching, parasitic layout concepts, and custom silicon structures..
• Debugging skills in physical verification (LVS, DRC, and DFM) using industry-standard verification engines (such as Calibre or ICV), with a proven ability to solve complex, systemic layout errors.
• Tcl, Python, or SKILL to automate layout creation, checking, and full-chip database manipulation.

Preferred Qualifications and Experience:

Experience