IC Layout Engineer: AI & Datacenter Hardware Analysis

SemiAnalysis; Hillsboro (OR); Hybrid; USD 120,000 - 180,000; Full time

Job summary

SemiAnalysis is seeking an experienced IC Layout Engineer in Hillsboro, OR to analyze physical design, layout, and manufacturing implementations of AI and datacenter hardware. You will examine die-level evidence, identify architectural implications, and report findings to the lab and stakeholders.

You will collaborate with a globally distributed team, drive end-to-end teardown, and contribute to DTCO/STCO reasoning, layout optimization, and technical publications.

Qualifications

• 2+ years of industry experience in IC layout or physical design preferred.
• Strong understanding of digital and/or analog physical design flows on advanced nodes.
• Exposure to standard-cell architectures and area/power/performance optimization.
• Experience with reading GDS/OASIS-level detail and layout evidence.

Responsibilities

• Conduct detailed physical design and layout analysis of AI/datacenter hardware, including GPUs, ASICs, CPUs, accelerators, high-speed I/O, memory subsystems, and packaging.
• Perform floorplan analysis: identify blocks, partitioning strategy, hierarchy, power distribution, and I/O placement from die imagery.
• Assess standard-cell libraries, cell utilization, placement density, and optimization strategies across designs.
• Analyze analog/mixed-signal layout regions and interpret matching, isolation, and routing choices.
• Drive teardown and characterization; operate the analytical toolchain and coordinate specialized work.
• Identify competitive advantages and changes in physical design, packaging, and system decisions.
• Apply DTCO/STCO reasoning to interpret layout trade-offs and process-design interactions.
• Co-author technical research publications and contribute to lab capabilities expansion.
• Collaborate across a globally distributed team to translate findings into strategic insights.

Skills

IC layout

Digital/analog layout

Floorplanning

DTCO/STCO concepts

Python for data analysis

GDS/OASIS reading

AI hardware understanding

Tools

Innovus

Fusion Compiler

Virtuoso

Job description

SemiAnalysis is seeking an experienced IC Layout Engineer in Hillsboro, OR to analyze physical design, layout, and manufacturing implementations of AI and datacenter hardware. You will examine die-level evidence, identify architectural implications, and report findings to the lab and stakeholders.

You will collaborate with a globally distributed team, drive end-to-end teardown, and contribute to DTCO/STCO reasoning, layout optimization, and technical publications.