Senior SoC Full-Chip Layout & Integration Engineer

Intel; Austin (TX); Hybrid; USD 122,000 - 232,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Hybrid work model

Job summary

Intel Foundry's Design Technology Platform (DTP) team is seeking an experienced engineer to lead full-chip floorplanning, integration, and tapeout for advanced-node silicon development vehicles. You will develop custom layout methodologies and drive verification and tapeout execution for cutting-edge process technologies.

Join a collaborative team working at the intersection of technology development, physical design, and manufacturing.

Qualifications

• Masters' degree in Electrical Engineering, Computer Engineering, or a related field with 4+ years of industry experience. OR a PhD’s degree in the same field with 1+ years of industry experience.
• Custom/analog/mixed-signal layout design experience in advanced technology nodes.
• Front-end (FEOL) layout design rules, transistor-level matching, parasitic layout concepts, and custom silicon structures.
• Debugging skills in physical verification (LVS, DRC, and DFM) using industry-standard verification engines (Calibre or ICV).
• Tcl, Python, or SKILL to automate layout creation, checking, and full-chip database manipulation.

Responsibilities

• Lead full-chip floorplanning, physical integration, and tapeout activities for advanced-node silicon development vehicles.
• Develop and enhance custom layout methodologies and physical design flows.
• Drive physical verification closure, including DRC, LVS, DFM, density, and antenna rule compliance.
• Collaborate with Technology Development, PDK, and EDA teams to implement scalable and manufacturable design solutions.
• Analyze advanced-node design rules and contribute to design enablement for emerging process technologies, including FinFET and Gate-All-Around (GAA) architectures.
• Coordinate cross-functional activities to ensure tape-in readiness, database integrity, and successful project execution.

Skills

Layout design

FEOL design rules

Physical verification debugging

Automation scripting

Education

Master's degree in Electrical/Computer Engineering or related field

Tools

Cadence Virtuoso

Calibre

Job description

Intel Foundry's Design Technology Platform (DTP) team is seeking an experienced engineer to lead full-chip floorplanning, integration, and tapeout for advanced-node silicon development vehicles. You will develop custom layout methodologies and drive verification and tapeout execution for cutting-edge process technologies.

Join a collaborative team working at the intersection of technology development, physical design, and manufacturing.