Senior SoC Full-Chip Layout & Integration Architect

Intel Corporation; Phoenix (AZ); Hybrid; USD 122,000 - 232,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

401(k) retirement plan

Vacation

Job summary

Intel Corporation seeks an experienced engineer to join the X-Chip Full-Chip Integration team within the Design Technology Platform. You will lead full-chip floorplanning, develop custom layout methods, and drive verification and tapeout for advanced-node silicon development vehicles across US sites.

You will collaborate with PDK, Technology Development, and EDA teams; automate layout tasks with Tcl, Python, or SKILL to boost productivity and quality.

Qualifications

• Masters’ degree in Electrical Engineering, Computer Engineering, or related field with 4+ years of industry experience.
• PhD with 1+ year of industry experience.
• Experience in custom/analog/mixed-signal layout design in advanced technology nodes.
• Experience with DRC, LVS, DFM verification and full-chip database tooling (Calibre or ICV).

Responsibilities

• Lead full-chip floorplanning, physical integration, and tapeout activities for advanced-node silicon development vehicles.
• Develop and enhance custom layout methodologies and physical design flows.
• Drive physical verification closure including DRC, LVS, DFM, density, and antenna checks.
• Collaborate with PDK, Technology Development, and EDA teams to implement scalable design solutions.

Skills

Custom layout design

Physical design flows

Automation scripting

Cross-functional collaboration

Education

Masters in Electrical/Computer Engineering

PhD with industry experience

Tools

Cadence Virtuoso

Calibre

ICV

Job description

Intel Corporation seeks an experienced engineer to join the X-Chip Full-Chip Integration team within the Design Technology Platform. You will lead full-chip floorplanning, develop custom layout methods, and drive verification and tapeout for advanced-node silicon development vehicles across US sites.

You will collaborate with PDK, Technology Development, and EDA teams; automate layout tasks with Tcl, Python, or SKILL to boost productivity and quality.