Machine Learning SoC Architect

Meta; Sunnyvale (CA); Hybrid; USD 260,000 - 420,000; Full time

Job summary

Meta is seeking a Machine Learning SoC Architect within the Silicon Engineering organization to define and drive architectural definitions, performance analysis, and pre-silicon modeling for custom ASICs powering Meta's AI/ data center workloads at scale.

The role requires 12+ years in architecture and performance, proficiency in C++/Python for modeling, and collaboration across architecture, RTL, and physical design teams to achieve hyperscale throughput and efficiency targets.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
• 12+ years of prior experience in defining and delivering multiple high performance ASICs into production, with focus on architecture definition and performance analysis.
• Experience in ASIC performance modeling, microarchitectural analysis, or pre-silicon simulation for custom silicon or SoC designs.
• Proficiency in C++ and Python for developing simulation models, automation frameworks, and performance analysis tools.
• Experience with performance analysis of data center, AI accelerator, or high-performance computing workloads on custom silicon.
• Experience defining architecture and microarchitectural specifications and driving cross-functional alignment across architecture, RTL, and physical design teams.
• Familiarity with post-silicon performance validation and model-to-hardware correlation methodologies.
• Programming in C or C++ with knowledge of mapping hardware algorithms to efficient C/C++ code.
• Master's or PhD degree in Electrical Engineering, Computer Engineering or related field.
• Domain knowledge in power/performance tradeoffs, ML networks, ML frameworks such as Pytorch.
• Experience building or scaling performance modeling infrastructure for hyperscale data center ASICs, including network, storage, or AI inference accelerator designs.

Responsibilities

• Define and drive architectural definition, performance analysis, and pre-silicon modeling for custom ASICs.
• Own architecture specification and performance modeling methodology and silicon roadmap strategy.
• Collaborate with silicon, RTL, and physical design teams to meet throughput, latency, and efficiency targets.
• Develop simulation models, automation tools, and performance analysis frameworks.
• Address data center, AI accelerator, or HPC workloads on custom silicon.

Skills

Computer Architecture

Microprocessor Architecture

Memory Systems

On-Chip Interconnect

Hardware/Software Partitioning

ASIC Performance Modeling

Pre-Silicon Simulation

C/C++

Python

Data Center Workloads

Cross-Functional Alignment

RTL

Physical Design

Post-Silicon Validation

ML/AI Frameworks

Education

Bachelor's degree

Master's or PhD in EE/CE

Tools

C++

Python

Job description

Meta is seeking a Machine Learning SoC Architect for its Silicon Engineering organization responsible for building custom silicon solutions that power the infrastructure underpinning Meta's AI and data center workloads at scale. As an ASIC Engineer specializing in architecture, performance and modeling, you will define and drive the architectural definition, performance analysis, pre-silicon modeling, and microarchitectural exploration of custom ASICs designed for Meta's Data Centers. In this role, you will own ASIC architecture specification, establish the performance modeling methodology and long-term silicon roadmap strategy, partnering with other silicon, and software teams to ensure Meta's infrastructure silicon meets the demanding throughput, latency, and efficiency targets required at hyperscale.

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• Experience and knowledge of Computer Architecture concepts such as microprocessor architecture, memory systems, on-chip interconnection networks, hardware/software partitioning etc
• 12+ years of prior experience in defining and delivering multiple high performance ASICs into production, with focus on architecture definition and performance analysis
• Experience in ASIC performance modeling, microarchitectural analysis, or pre-silicon simulation for custom silicon or SoC designs
• Proficiency in C++ and Python for developing simulation models, automation frameworks, and performance analysis tools
• Experience with performance analysis of data center, AI accelerator, or high-performance computing workloads on custom silicon
• Experience defining architecture and microarchitectural specifications and driving cross-functional alignment across architecture, RTL, and physical design teams
• Familiarity with post-silicon performance validation and model-to-hardware correlation methodologies
• Programming in C or C++ with knowledge of mapping hardware algorithms to efficient C/C++ code
• Master's or PhD degree in Electrical Engineering, Computer Engineering or related field
• Domain knowledge in one or more of power/performance tradeoffs, ML networks, ML frameworks such as Pytorch
• Experience building or scaling performance modeling infrastructure for hyperscale data center ASICs, including network, storage, or AI inference accelerator designs