Senior PCIe SV-UVM Verification Engineer | Equity Eligible

Credo; San Jose (CA); On-site; USD 138,000 - 218,000; Full time

Job summary

Credo is seeking a Senior Design Verification Engineer to ensure the quality and performance of complex digital designs through rigorous verification. You will develop verification plans, build scalable testbenches, and write SV-UVM sequences while collaborating with RTL designers and firmware teams.

The role emphasizes PCIe verification, RTL design proficiency, and strong debugging. You will contribute to flexible verification workflows and drive silicon quality across HW/SW interfaces.

Qualifications

• BS/MS in Electrical Engineering or Computer Engineering with 7+ years in RTL and SV-UVM verification.
• PCIe verification experience with gate-level and firmware-based simulation.
• Proficiency in RTL design and computer architecture concepts.
• Strong debugging, problem-solving, and analytical skills.

Responsibilities

• Develop verification and test plans; build reusable SV-UVM testbenches and sequences.
• Verify PCIe subsystems and interfaces (I2C/I3C/SMBus/UART/SPI) at block/subsystem levels.
• Write assertions, checkers, and coverage; analyze gaps and drive closure.
• Build firmware-based simulations in C to mirror FW behavior for HW/SW verification.
• Automate flows with Python; collaborate with AEs and FW teams on DV findings.

Skills

SV-UVM

RTL verification

PCIe verification

Debugging

Problem solving

Python scripting

FW interaction

Education

BS/MS in Electrical or Computer Engineering

Job description

Credo is seeking a Senior Design Verification Engineer to ensure the quality and performance of complex digital designs through rigorous verification. You will develop verification plans, build scalable testbenches, and write SV-UVM sequences while collaborating with RTL designers and firmware teams.

The role emphasizes PCIe verification, RTL design proficiency, and strong debugging. You will contribute to flexible verification workflows and drive silicon quality across HW/SW interfaces.