Senior SoC Architect: Memory Subsystem & DRAM Controller

Samsung-Research-America; Mountain View (CA); On-site; USD 272,489,280 - 408,596,160; Full time

Job summary

Samsung Research America is seeking a Senior Staff Engineer, SoC Architecture focusing on Memory Subsystem and Interconnect. This role is crucial for architecting next-generation SOCs, leading projects on Fabric, Cache, and DRAM controllers to enhance performance and power efficiency.

The ideal candidate will have over 9 years in SOC design, deep experience with memory architectures and standards, as well as a relevant degree in Computer Science or Engineering.

Qualifications

• 9+ years of experience in SOC or ASIC design and architecture.
• Prior direct experience in Fabric, System Cache, DRAM controller architecture or microarchitecture.
• Understanding of memory controller architecture and memory scheduling.

Responsibilities

• Guide development of innovative Fabric, System cache and DRAM controller features.
• Evaluate architecture proposal benefits and communicate results.
• Perform high-level performance modeling of Fabric, System cache and DRAM controller features.

Skills

SoC or ASIC design and architecture

Fabric, System Cache, DRAM controller architecture

ARM bus infrastructure (ACE/AXI/AHB)

JEDEC standards (LPDDR, DDR, HBM)

Performance modeling/simulation

Education

BSc, Masters, or PhD in Computer Science/Engineering

Tools

BookSim Simulator

Platform Architect

Job description

Samsung Research America is seeking a Senior Staff Engineer, SoC Architecture focusing on Memory Subsystem and Interconnect. This role is crucial for architecting next-generation SOCs, leading projects on Fabric, Cache, and DRAM controllers to enhance performance and power efficiency.

The ideal candidate will have over 9 years in SOC design, deep experience with memory architectures and standards, as well as a relevant degree in Computer Science or Engineering.