Senior Silicon DFT Engineer, SERDES & SoC Testing

MatX; Mountain View (CA); Hybrid; USD 160,000 - 600,000; Full time

Benefits offered by this job

PTO 4 weeks

Holidays 12

Remote work up to 3 weeks

Job summary

MatX is building a silicon-centric GenAI compute platform and seeks a Silicon DFT engineer to implement DFT functions across SERDES, boundary scan, and test modes for MatX products.

You will collaborate with verification and firmware teams to bring up silicon test programs from simulation to ATE, drive sign-off for DFT, and support root-cause analysis of test escapes while expanding DFT coverage.

Qualifications

• MBIST and at-speed scan experience.
• Knowledge of JTAG (IEEE 1149.1) and IJTAG (IEEE 1687) standards.
• Experience with loading and validating PHY firmware via SPI/I2C/JTAG, including bootloader sequences.

Responsibilities

• Design and develop functional test solutions for SERDES PHY, covering loopback and margin testing.
• DFT integration of PHY IP blocks and test pattern porting from IP to SoC-level.
• Develop firmware loading flows for PHY bring-up and test (SPI/JTAG).
• Collaborate with verification and firmware teams to bring up silicon test programs.

Skills

MBIST

At-speed scan

JTAG 1149.1

IJTAG 1687

SSN

SPI/JTAG firmware loading

Tools

Synopsys DFT Compiler

Mentor Tessent

Job description

MatX is building a silicon-centric GenAI compute platform and seeks a Silicon DFT engineer to implement DFT functions across SERDES, boundary scan, and test modes for MatX products.

You will collaborate with verification and firmware teams to bring up silicon test programs from simulation to ATE, drive sign-off for DFT, and support root-cause analysis of test escapes while expanding DFT coverage.