Silicon DFT Engineer — Remote, Equity

MatX Inc.; Mountain View (CA); Híbrido; USD 160.000 - 600.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Time off: 4 weeks PTO+ holidays

Health insurance

Remote work up to 3 weeks

401K

Parental leave

Mental health support

Descripción de la vacante

MatX Inc. is building a cutting-edge silicon design-for-test (DFT) engineering team in Mountain View to enable high-performance GenAI silicon.

You will implement DFT functions for SERDES PHY, integrate DFT patterns, and develop firmware loading flows for PHY bring-up, collaborating across verification, firmware, and test teams to ensure robust silicon test programs from simulation to ATE. Ideal candidates have hands-on DFT experience (MBIST, at-speed test), knowledge of JTAG/IJTAG, and

Formación

• Hands-on experience implementing DFT functions for silicon, including MBIST, at-speed scan, and scan compression.
• Experience integrating PHY DFT interfaces (SERDES test modes, analog test buses) into SoC DFT architecture.
• Familiarity with bootloader sequences and register map initialization for PHY firmware loading.

Responsabilidades

• Design and implement functional test solutions for SERDES PHY, including loopback and eye diagram characterization.
• Perform DFT integration of PHY IP blocks and develop robust test pattern porting from IP to SoC.
• Develop firmware loading flows for PHY bring-up via SPI/JTAG and support test program debug.

Conocimientos

DFT implementation

JTAG (IEEE 1149.1)

IJTAG (IEEE 1687)

Streaming Scan Networks

SERDES PHY test

Herramientas

Synopsys DFT Compiler

Mentor Tessent

Descripción del empleo

MatX Inc. is building a cutting-edge silicon design-for-test (DFT) engineering team in Mountain View to enable high-performance GenAI silicon.

You will implement DFT functions for SERDES PHY, integrate DFT patterns, and develop firmware loading flows for PHY bring-up, collaborating across verification, firmware, and test teams to ensure robust silicon test programs from simulation to ATE. Ideal candidates have hands-on DFT experience (MBIST, at-speed test), knowledge of JTAG/IJTAG, and