Senior Signal Integrity Architect - Interface Pathfinding

Micron Technology, Inc.; Folsom (CA); On-site; USD 119,000 - 320,000; Full time

Benefits offered by this job

Medical/Dental/Vision benefits

Paid time off

Equity

Job summary

Micron Technology, Inc. seeks a Principal Signal Integrity Engineer to drive high‑speed interface analysis across packaging and interconnects. You will own models from field solver extraction to circuit simulation, guiding design decisions with rigorous SI methods.

You will collaborate with SI, circuit/chip design, packaging R&D, and system teams to push forward‑looking SI solutions for memory interfaces, while mentoring newer engineers and documenting methodologies.

Qualifications

• MS or PhD in Electrical Engineering or related field; MS accepted with strong SI fundamentals.
• 10+ years of experience in signal or power integrity analysis for high‑speed interfaces.
• Expert in electromagnetic and transmission line theory applied to SI/PI.
• Proficient with time- and frequency-domain simulators and EM solvers.
• Hands‑on hardware measurement experience (scope, TDR, VNA).
• Strong written and verbal communication; cross‑organisational collaboration.

Responsibilities

• Own generation and validation of interconnect models from extraction to simulation.
• Lead SI assessment of forward‑looking substrates and packaging technologies.
• Drive SI analysis during pathfinding studies and IO/channel co‑optimization.
• Develop progressive design rules for package and system‑level performance.
• Define link budgets and sim‑to‑silicon correlation methodologies.

Skills

Signal Integrity

EM Theory

SI Simulation

Cross-disciplinary Collaboration

Strong Communication

Education

MS in Electrical Engineering

PhD in Electrical Engineering

Tools

ADS

HSPICE

SPECTRE

Q3D

SIWAVE

HFSS

Oscilloscope

TDR

VNA

Job description

Micron Technology, Inc. seeks a Principal Signal Integrity Engineer to drive high‑speed interface analysis across packaging and interconnects. You will own models from field solver extraction to circuit simulation, guiding design decisions with rigorous SI methods.

You will collaborate with SI, circuit/chip design, packaging R&D, and system teams to push forward‑looking SI solutions for memory interfaces, while mentoring newer engineers and documenting methodologies.