Senior SI Engineer - High-Speed Interfaces

Micron Technology, Inc; Boise (ID); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision plans

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. is seeking a Principal Signal Integrity Engineer to lead cutting‑edge SI analyses for high‑speed interfaces.

You will own interconnect modeling, channel optimization, and SI methodology development, collaborating with circuit, packaging, and system teams on forward‑looking solutions. The role emphasizes analytical leadership, modeling reports, and design rule development to ensure pre‑silicon confidence in next‑gen memory and die‑to‑die interfaces.

Qualifications

• MS or PhD in Electrical Engineering (MS accepted; PhD preferred).
• 10+ years of industry experience in signal/power integrity for high‑speed interfaces.
• Strong EM and transmission line theory applied to SI/PI analysis.
• Extensive experience with time‑ and frequency‑domain simulators (ADS, HSPICE, SPECTRE).
• Deep experience with EM solvers (Q3D, SIWAVE, HFSS) and setup/validation.
• Hands‑on hardware measurement exposure (oscilloscopes, TDR, VNA).
• Ability to own analyses, influence decisions, and communicate results clearly.

Responsibilities

• Lead original SI analysis for high‑speed interconnects and channel solutions.
• Develop and validate interconnect models from field solver extractions to circuit simulations.
• Drive substrate and packaging evaluation with signal integrity implications.
• Define design rules and budget methodologies to enable performance scaling.
• Collaborate across SI, circuit, packaging, and system teams to provide actionable guidance.

Skills

Signal integrity

Power integrity

Electromagnetic theory

Cross‑disciplinary collaboration

Written and verbal communication

Education

MS or PhD in Electrical Engineering

Tools

ADS

HSPICE

SPECTRE

Q3D

SIWAVE

HFSS

Job description

Micron Technology, Inc. is seeking a Principal Signal Integrity Engineer to lead cutting‑edge SI analyses for high‑speed interfaces.

You will own interconnect modeling, channel optimization, and SI methodology development, collaborating with circuit, packaging, and system teams on forward‑looking solutions. The role emphasizes analytical leadership, modeling reports, and design rule development to ensure pre‑silicon confidence in next‑gen memory and die‑to‑die interfaces.