Senior Signal Integrity Architect, Interface Pathfinding

Micron; Boise (ID); On-site; USD 170,000 - 250,000; Full time

Job summary

Micron Technology is seeking a Principal Signal Integrity Engineer to lead high-speed interface analysis and modeling efforts. You will drive interconnect modeling, substrate evaluation, and channel optimization, while coordinating across SI, circuit and packaging teams to deliver robust pre-silicon predictions.

You will own analysis methodologies, validate solver results, and champion design-rule development to enable scaling of performance in next‑gen memory interfaces.

Qualifications

• MS or PhD in Electrical Engineering or related field; hands-on modeling and simulation essential.
• 10+ years of industry experience in signal or power integrity for high-speed interfaces.
• Strong electromagnetics and transmission line theory applied to SI/PI.
• Experience with time- and frequency-domain tools and electromagnetic solvers.

Responsibilities

• Own interconnect modeling from extraction to circuit simulation and validate model quality.
• Lead SI assessment of forward-looking substrate and packaging technologies.
• Drive SI analysis during pathfinding studies; coordinate with other teams.
• Develop design rules for package and system-level performance scaling.
• Define link budgets and establish sim-to-silicon correlation methodologies.
• Collaborate across SI, Circuit & Chip Design, Packaging R&D and System Integration.
• Produce analysis reports, modeling docs, and design-rule specifications.

Skills

SI analysis

PI analysis

Electromagnetic theory

Transmission lines

Modeling & Simulation

Cross-functional collaboration

Decision making

Written communication

Education

MS or PhD in Electrical Engineering

Tools

ADS

HSPICE

SPECTRE

HFSS

Q3D

SIWAVE

Job description

Micron Technology is seeking a Principal Signal Integrity Engineer to lead high-speed interface analysis and modeling efforts. You will drive interconnect modeling, substrate evaluation, and channel optimization, while coordinating across SI, circuit and packaging teams to deliver robust pre-silicon predictions.

You will own analysis methodologies, validate solver results, and champion design-rule development to enable scaling of performance in next‑gen memory interfaces.