Senior SI/PI Engineer for AI/TPU Hardware

Google LLC; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google Sunnyvale, CA, USA seeks a Senior Signal and Power Integrity Engineer to shape AI/ML hardware acceleration. You will drive SI/PI for chip, package, and advanced 2.5D/3D packaging, partnering with cross-functional teams to optimize PDN, netlists, and routability from concept to production.

You will influence chip floorplanning, develop next-generation memory interfaces, and lead post-silicon validation for NPI, contributing to TPU architecture and integration within AI/ML systems.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field.
• 8+ years of SI/PI design experience for chip/package or system PCB.
• Experience with industry SIPI toolchains (HFSS/ADS/Sigrity/Siwave).
• Experience with lab bring-up, test environments, and characterization for high-speed memory and SerDes.

Responsibilities

• Lead SI/PI analysis and optimization for high-performance computing and TPU architecture.
• Partner early in product definition to influence floorplanning and PDN decisions.
• Evaluate high-speed interfaces and develop memory interfaces across IO PHY, SI/PI, and PD boundaries.
• Drive post-silicon validation and qualification for NPI within design constraints.
• Collaborate with silicon, system, and external vendor teams to advance modeling methods.

Skills

SI/PI design experience

Lab bring-up & characterization

Python/ MATLAB/ C++

Cross-team collaboration across chip/架

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Tools

HFSS

ADS

Sigrity

Siwave

Job description

Google Sunnyvale, CA, USA seeks a Senior Signal and Power Integrity Engineer to shape AI/ML hardware acceleration. You will drive SI/PI for chip, package, and advanced 2.5D/3D packaging, partnering with cross-functional teams to optimize PDN, netlists, and routability from concept to production.

You will influence chip floorplanning, develop next-generation memory interfaces, and lead post-silicon validation for NPI, contributing to TPU architecture and integration within AI/ML systems.