Silicon Packaging Engineer

Socket.dev; Sunnyvale (CA); On-site; USD 178,000 - 250,000; Full time

Job summary

Socket.dev is seeking a seasoned SI/PI Engineer to own chip-package-system co-design for AI accelerators and HPC silicon. You will drive SI/PI requirements from architecture through post-silicon validation across 2.5D/3D packaging with interposers, wafer-on-wafer stacking, and high-density substrates.

You will collaborate with ASIC, package, PCB, and foundry teams to ensure high-speed interfaces and PDN meet performance and reliability targets before tape-out.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 8+ years of experience with signal integrity analysis, simulation, and measurement
• Proficient with HFSS, Sigrity, Hspice, and/or other simulation tools
• Familiar with impedance control, transmission line and PDN characterization, feasibility study and design guidelines
• Experience with 2.5D/3D package design (e.g., silicon interposer, silicon bridge, 3D die stacking, STA, voltage budget, simulation)
• Expertise in signal and power integrity for various high speed interconnects (HBMx, D2D, Ethernet, PCIe)
• Familiarity with post-Si test environment on memory and high-speed SERDES
• Familiarity with next-gen memory, chiplet standards and timing budgets
• Package-level SI/PI understanding across silicon, package, and board

Responsibilities

• Chip-Package-System Co-Design: drive SI/PI requirements from product definition to tape-out
• Die-Package-Board Co-Optimization across multiple chiplets
• Package SI/PI Ownership: substrate/interposer stack-up selection, design guide, post-layout sign-off
• High-Speed Interfaces: manage channels for HBM/HBM4/UHBM, UCIe, PCIe, Ethernet SerDes
• Power Delivery: analyze PDN AC+DC, impedance, decoupling, IR drop
• Simulation Flow: lead pre/post-layout SI/PI simulations and model development
• Timing & Budgets: maintain interface timing and voltage/noise budgets
• Tool & Flow Development: improve SI/PI flows via automation and modeling
• Validation Methodology: define SI/PI validation plans
• Post-Silicon: post-silicon validation and lab correlation
• Failure Analysis: support design validation on SI/PI failures
• Cross-functional collaboration across Architecture, ASIC, Mixed Signal, Package, PCB
• Engage foundries and OSATs on interconnect and die-stacking standards

Skills

Signal integrity

Power integrity

2.5D/3D package design

Impedance control

Transmission line theory

Education

Bachelor's degree in CS/CE or equivalent

Tools

HFSS

Sigrity

HSPICE

Job description

We are seeking a highly skilled Signal Integrity and Power Integrity (SI/PI) Engineer to own chip-package-system co-design for next-generation AI accelerator and high-performance computing silicon. In this role you will drive SI/PI requirements from architecture definition through post-silicon validation across 2.5D/3D heterogeneous packages - silicon interposer, RDL fan-out, wafer-on-wafer die stacking, and high-density organic substrates. You will work closely with ASIC architecture, physical design, package layout, PCB, and foundry/OSAT partners to ensure high-speed interfaces and power delivery networks meet performance, margin, and reliability targets before tape-out and Gerber release.

Responsibilities

• Chip-Package-System Co-Design: Drive SI/PI requirements analysis and optimization into product definition - chip floorplan, bump map, power tree structure, and net topology - for HPC and AI silicon built on 2.5D/3D package technology.
• Die-Package-Board Co-Optimization (DPCO): Partner with package layout and physical design to converge bump assignment, escape routing, and stack-up decisions across multiple disparate chiplets.
• Package SI/PI Ownership: Lead ASIC package SI/PI design activities including substrate and interposer stack-up and material selection, design guide authoring, layout review, and post-layout sign-off.
• High-Speed Interfaces: Own channel design and margining for HBM/HBM4/UHBM, UCIe and other die-to-die links, PCIe Gen 5/Gen 6, Ethernet SerDes, and next-generation memory interfaces.
• Power Delivery: Execute package and board PDN AC+DC analysis for low-voltage/high-current supplies, including impedance targeting, decoupling optimization, IR drop, and di/dt noise.
• Simulation Flow: Lead pre-layout and post-layout simulation flows for high-speed I/O and PDN; build simulation models and develop reusable SI/PI methodology.
• Timing & Budgets: Develop and maintain interface timing budgets and voltage/noise budgets spanning silicon IO PHY, package, and board.
• Tool & Flow Development: Improve the accuracy and turnaround time of SI/PI flows through automation and correlation-driven model refinement.
• Validation Methodology: Define SI/PI validation methodology and detailed engineering test plans.
• Post-Silicon: Conduct post-silicon validation and qualification of high-speed interfaces; measure PDN impedance and channel performance in the lab and correlate against simulation.
• Failure Analysis: Support Design Validation teams on SI/PI failure analysis and drive corrective design guidance back into the flow.
• Work across Architecture, ASIC, Mixed Signal, Package, PCB, and System teams to ensure package and system SI/PI performance meets expectation before Gerber out.
• Engage foundries and OSATs (e.g., TSMC CoWoS/SoIC, Intel EMIB) and memory suppliers on emerging interconnect and die-stacking standards.

Minimum Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 8+ years of experience with signal integrity analysis, simulation, and measurement
• Proficient with HFSS, Sigrity, Hspice, and/or other simulation tools
• Proven understanding of impedance control, transmission line and PDN characterization, feasibility study and create practical design guidelines
• Experience with 2.5D/3D package design (e.g., silicon interposer, silicon bridge, 3D die stacking, STA, Voltage budget, complex SIPI models, frequency, and time domain simulation)
• Expertise in signal and power integrity for various high speed interconnects (e.g., HBMx, D2D, Ethernet, PCIe and etc)
• Familiarity with post-Si test environment on memory (HBM/ /DDR4/LPDDR4/DDR5/LPDDR5) or high speed SERDES
• Familiarity to next generation memory and chiplet standards and timing budget methodology
• Package-level signal integrity and power integrity understanding including silicon, package, and board

Preferred Qualifications

• 10+ years of experience in SIPI simulation and validation areas
• Master degree or PhD in Electrical Engineering, Physics, Mathematics, or related field
• Experience with high-speed interface protocols such as MIPI, PCIe, memory, HBMand USB
• Experience using Cadence Sigrity, PowerSI, Ansys SIwave, Keysight ADS, 3D layout and Ansys HFSS
• Experience with consumer hardware design, review and bring-up process, CAD tools, constraint manager etc
• 8+ years of experience in SIPI fundamentals, familiar with substrate/PCB design and manufacture process
• Experience in collaborating with cross-functional teams, including chip top design, physical design, Static Timing Analysis (STA), package, and system teams
• Solid understanding and experiences in computational electromagnetics and transmission line theory

$178,000/year to $250,000/year + bonus + equity + benefits