Senior SerDes & DSP Systems Architect

Synopsys, Inc.

Sunnyvale, Northern (CA, KY)

Hybrid

USD 170,000 - 260,000

Full time

14 days+

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Job summary

Synopsys, Inc. in Sunnyvale, CA, seeks an accomplished engineer to lead SerDes system modeling and high-speed transceiver development. You will run comprehensive simulations, design advanced calibration algorithms, and correlate results with silicon measurements across PCIe and Ethernet protocols.

The role requires 13+ years in EE with M.Sc or Ph.D and strong MATLAB/Simulink modeling. Collaborate across analog, digital, and hardware teams, support customers, and help push silicon IP to new

Qualifications

MSc or PhD in Electrical or Computer Engineering
Strong MATLAB/Simulink modeling skills
Solid DSP and communications theory knowledge
Experience with high-speed SerDes design
Familiarity with PCIe, Ethernet, JESD204C, CPRI protocols
C/Verilog-A/SystemVerilog and Python programming

Responsibilities

Develop SerDes system models for PAM4 transceivers targeting PCIe (128Gbps+) and Ethernet (200Gbps+) standards
Run comprehensive system simulations to verify and sign-off design performance across protocols and channels
Design and propose advanced algorithms to calibrate and adapt transceivers for optimal performance
Correlate simulated performance with silicon measurements for accuracy and reliability
Provide expert assistance to customers for system-level performance issues and troubleshooting
Collaborate with cross-functional teams of analog, digital, and hardware engineers throughout development and post-silicon

Job description

The role requires 13+ years in EE with M.Sc or Ph.D and strong MATLAB/Simulink modeling. Collaborate across analog, digital, and hardware teams, support customers, and help push silicon IP to new

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