Senior SerDes/DSP Systems Architect (PAM4)

Synopsys Inc; Sunnyvale (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Synopsys Inc. is seeking an accomplished engineer to lead SerDes modeling and high‑speed transceiver development for PAM4 interfaces.

You will collaborate with analog, digital, and hardware teams to ensure silicon IP excellence and robust system performance across PCIe and Ethernet standards. The role emphasizes rigorous simulations, algorithm development for calibration, and close ties to silicon validation and customer support, with opportunities to mentor peers and drive innovations in

Qualifications

• M.Sc. or Ph.D. in Electrical or Computer Engineering with 13+ years of relevant experience.
• Strong experience modeling circuits and systems in MATLAB/Simulink.
• Solid understanding of DSP and communications theory, including equalization, encoding, and noise/crosstalk filtering.
• Proficiency in analyzing link budgets for PAM4 high-speed serial links and familiarity with wireline and optical protocols.

Responsibilities

• Developing and maintaining SerDes system models for PAM4 transceivers targeting PCIe (128Gbps+) and Ethernet (200Gbps+) standards.
• Running comprehensive system simulations to verify and sign‑off design performance across multiple protocols and channels.
• Designing and proposing advanced algorithms to calibrate and adapt transceivers for optimal performance.
• Correlating simulated performance with silicon measurements to ensure accuracy and reliability.
• Providing expert assistance to customers for system‑level performance issues and troubleshooting.
• Collaborating with cross‑functional teams of analog, digital, and hardware engineers throughout all stages of development and post‑silicon.
• Contributing to lab testing and analysis for high‑speed serial links, ensuring robust design validation.

Skills

MATLAB/Simulink modeling

DSP & communications theory

PAM4 SerDes design

C/Verilog‑A/SystemVerilog

Python programming

High-speed SerDes knowledge

Education

M.Sc. or Ph.D. in Electrical or Computer Engineering

Tools

MATLAB/Simulink

Verilog/SystemVerilog

Python

Job description

Synopsys Inc. is seeking an accomplished engineer to lead SerDes modeling and high‑speed transceiver development for PAM4 interfaces.

You will collaborate with analog, digital, and hardware teams to ensure silicon IP excellence and robust system performance across PCIe and Ethernet standards. The role emphasizes rigorous simulations, algorithm development for calibration, and close ties to silicon validation and customer support, with opportunities to mentor peers and drive innovations in