SerDes Systems Architect — High-Speed Analog & DSP Lead

Synopsys, Inc.; Boxborough (MA); On-site; USD 190,000 - 250,000; Full time

Job summary

Synopsys, Inc. is seeking a highly experienced Architect for SerDes IP with broad expertise in analog/mixed-signal design and DSP theory.

You will own end-to-end architecture for PAM4 transceivers, model systems, and drive calibration algorithms while coordinating with analog, digital RTL, and layout teams to deliver silicon-proven IP. Applicants should hold a PhD or MSc with substantial SerDes background, and be adept with MATLAB/Simulink, SPICE tools, and Verilog-A/SystemVerilog.

Qualifications

• PhD with 10+ years, or MSc with 12+ years of SerDes/high-speed analog and mixed-signal design experience.
• Silicon-proven, transistor-level design experience in TX, RX, and clock paths within SerDes architectures.
• In-depth knowledge of SerDes sub-circuits such as equalizers, samplers, drivers, serializers/deserializers, VCOs, phase interpolators, PLLs, ADCs, and DACs.
• Strong DSP and communications theory knowledge, including equalization, encoding, and noise/crosstalk filtering.
• Experience with MATLAB/Simulink modeling and link budgets for PAM4 links.
• Familiarity with wireline (PCIe, Ethernet, JESD204C, CPRI) and optical (LINEAR, RTLR) protocols.

Responsibilities

• Own the architecture of SerDes IP for PAM4 transceivers targeting PCIe (128Gbps+) and Ethernet (200Gbps+).
• Interpret SerDes standards and develop system models and link budgets translating into analog/DSP specs.
• Lead design of analog macro-level circuits across TX, RX and clock paths, balancing power, area and performance.
• Run comprehensive system and circuit simulations to verify design performance across protocols.
• Design calibration/adaptation/control algorithms and collaborate with digital RTL engineers.
• Oversee physical layout to minimize parasitics and process variation impacts.
• Correlate simulated performance with silicon measurements and contribute to lab testing.
• Track progress of sub-block owners and junior engineers; mentor where needed.
• Present technical insights during peer/customer reviews and support system-level issues.
• Document design features, methodologies, and test plans for internal and customer use.

Skills

SerDes architecture

Analog/mixed-signal design

DSP theory

MATLAB/Simulink

Verilog-A/SystemVerilog

Python/C/TCL

Education

PhD

MSc

Tools

SPICE simulators

EDA tools

Job description

Synopsys, Inc. is seeking a highly experienced Architect for SerDes IP with broad expertise in analog/mixed-signal design and DSP theory.

You will own end-to-end architecture for PAM4 transceivers, model systems, and drive calibration algorithms while coordinating with analog, digital RTL, and layout teams to deliver silicon-proven IP. Applicants should hold a PhD or MSc with substantial SerDes background, and be adept with MATLAB/Simulink, SPICE tools, and Verilog-A/SystemVerilog.