Lead SerDes Validation Engineer (112G/224G PAM4)

Entrada Ventures; Palo Alto (CA); Hybrid; USD 180,000 - 260,000; Full time

Benefits offered by this job

Equity

Benefits

401(k)

Job summary

Entrada Ventures in Silicon Valley seeks a SerDes Validation Lead to own physical-layer implementation, tuning, and post-silicon validation of ultra-high-speed data links (112G and 224G PAM4). You will collaborate with signal integrity, power integrity, hardware and firmware teams to optimize link performance.

The role demands hands-on SerDes IP bring-up, extensive lab characterization, and development of automated test flows using Python. Equity and a growth-minded environment are offered.

Qualifications

• Hands-on experience bringing up 56G/112G/224G PAM4 links.
• Experience with PCIe Gen5/Gen6 is desirable.
• Understanding of TX/RX equalization effects on SI, jitter, eye margin, BER.

Responsibilities

• Drive implementation and register-level configuration of high-speed SerDes IP blocks across custom hardware systems.
• Own transceiver equalization tuning, including CTLE, FFE, and DFE tap optimization.
• Lead post-silicon physical-layer bring-up, characterization, and debugging of 112G and 224G PAM4 links.
• Use high-bandwidth oscilloscopes, BERTs, pattern generators, and protocol analyzers to validate link performance.
• Collaborate with SI/PI engineers to correlate lab measurements with layout and models.
• Work with firmware teams to support real-time link monitoring and automated validation flows.
• Develop and run script-based lab automation for test/measurement workflows.
• Define best practices for SerDes bring-up, tuning, and validation across hardware platforms.

Skills

SerDes implementation

Physical-layer debugging

Lab automation with Python

Oscilloscope & BERT proficiency

Collaboration with SI/PI teams

Firmware integration

Testing automation scripting

Tools

BERTs

Oscilloscopes

Pattern generators

Protocol analyzers

Python scripting

Job description

Entrada Ventures in Silicon Valley seeks a SerDes Validation Lead to own physical-layer implementation, tuning, and post-silicon validation of ultra-high-speed data links (112G and 224G PAM4). You will collaborate with signal integrity, power integrity, hardware and firmware teams to optimize link performance.

The role demands hands-on SerDes IP bring-up, extensive lab characterization, and development of automated test flows using Python. Equity and a growth-minded environment are offered.