Senior PHY & SerDes Architect (112/224 Gb/s PAM4)

Synopsys Inc; Sunnyvale (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Synopsys Inc. seeks an experienced PHY and SerDes architect in Sunnyvale, CA, to own high‑speed PAM4 PHY architecture and data paths. You will balance power, performance, area, latency, and reliability while coordinating across analog, digital, verification, and packaging teams.

The role requires deep expertise in 112/224 Gb/s PAM4 links, link budgeting, modeling, and calibration. You will guide architecture sign-off and contribute to differentiating high‑performance IP for silicon applications.

Qualifications

• Strong architectural knowledge of 112 Gb/s and 224 Gb/s PAM4 serial links.
• Expertise in link budgeting, insertion and return loss, crosstalk, jitter, BER, channel operating margin, and FEC coding gain.
• Deep knowledge of CTLE, FFE, DFE, ADC-DSP, PLL, CDR, adaptation, and calibration.
• Experience with channel and behavioral modeling, process-corner analysis, and analog, digital, and package PPA tradeoffs.

Responsibilities

• Own the PHY architecture, including protocols, data rates, BER, and PPA targets.
• Define data-path and clocking architectures, including modulation, equalization, FEC placement, ADC-DSP, PLL, and CDR.
• Lead calibration and adaptation strategies across process, voltage, temperature, and channel conditions.
• Allocate power, area, performance, and latency across analog, digital, and package components.
• Develop block specifications that engineering teams can implement and verify.
• Close the end-to-end link budget across the transmitter, package, channel, and receiver.
• Define architecture sign-off, modeling, observability, and silicon bring-up requirements, including loopback, PRBS, eye scan, and calibration access.
• Align standards, signal and power integrity, package, and program teams on guaranteed IP performance.

Skills

PAM4 PHY design

High-speed links

Link budgeting

Silicon bring-up

Tools

PRBS

Eye scan

Loopback

Job description

Synopsys Inc. seeks an experienced PHY and SerDes architect in Sunnyvale, CA, to own high‑speed PAM4 PHY architecture and data paths. You will balance power, performance, area, latency, and reliability while coordinating across analog, digital, verification, and packaging teams.

The role requires deep expertise in 112/224 Gb/s PAM4 links, link budgeting, modeling, and calibration. You will guide architecture sign-off and contribute to differentiating high‑performance IP for silicon applications.